Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Template dialog box. Use the different tabs of this dialog box to set the options described in this section.
Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.
Use the Virtex General tab, shown in the following figure, to set the general simulation options.
Figure 5.17 Virtex Simulation Template General Tab |  |
The Virtex General tab is identical to the tab described in the “Spartan General Tab” section.
Use the Virtex VHDL/Verilog tab, shown in the following figure, to set the VHDL or Verilog options.
Figure 5.18 Virtex Simulation Template VHDL/Verilog Tab | |
The Virtex VHDL/Verilog tab is identical to the tab described in the “Spartan VHDL/Verilog Tab” section.
Use the Virtex EDIF tab, shown in the following figure, to set the EDIF options.
Figure 5.19 Virtex Simulation Template EDIF Tab | |
The Virtex EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.
