Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Template dialog box. Use the different tabs of this dialog box to set the options described in this section.
Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.
Use the XC3000 General tab, shown in the following figure, to set the general simulation options.
Figure 5.27 XC3000 Simulation Template General Tab |  |
The XC3000 General tab is identical to the tab described in the “Spartan General Tab” section.
Use the XC3000 VHDL/Verilog tab, shown in the following figure, to set the VHDL or Verilog options.
Figure 5.28 XC3000 Simulation Template VHDL/Verilog Tab | |
This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The default name of the Global Set/Reset port depends on the target device family as described in the “Global Set/Reset Port Information” table.
Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.
By default, this option is off
This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension. By default, this option is off.
This option writes a library path pointing to the SIMPRIM library into the output Verilog (.v) file. The path is written as follows:
`uselib dir=$XILINX/verilog/data libext=.vmd
where $XILINX is the location of the Xilinx software. By default, this option is off.
This option is supported for Verilog only.
This option writes out a signal-to-pin mapping file. The file has a .pin extension. By default, this option is off.
This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy. By default, this option is off.
Use the XC3000 EDIF tab, shown in the following figure, to set the EDIF options.
Figure 5.29 XC3000 Simulation Template EDIF Tab | |
The XC3000 EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.
