The FPGA architecture consists of three types of configurable elements - a perimeter of input/output blocks (IOBs), a core array of configurable logic blocks (CLBs), and resources for interconnection. The IOBs provide a programmable interface between the internal array of logic blocks (CLBs) and the device's external package pins. CLBs perform user-specified logic functions, and the interconnect resources carry signals among the blocks.
A configuration program stored in internal static memory cells determines the logic functions and the interconnections. The configuration data is loaded into the device during power-up reprogramming functions.
FPGA devices are customized by loading configuration data into internal memory cells. The FPGA device can either actively read its configuration data out of an external serial or byte-wide parallel PROM (master modes), or the configuration data can be written to the FPGA device (slave and peripheral modes).
The Virtex devices support a fast, byte-wide “micro-controller friendly” configuration mode. For supported configuration modes of a specific family, refer to the Xilinx Programmable Logic Data Book or the device family data sheet.
The structure of CLBs varies from architecture to architecture. For information on a specific device, click one of the following architecture names.
XC3000 CLBs have two function generators for implementing combinatorial logic, two storage elements for requesting data, and an internal control section.
Each CLB includes five logic inputs, a common clock input, an asynchronous direct reset input, a clock enable, and two outputs. A data-in input is also provided for direct input to the flip-flops within the CLB.
The following figure illustrates the CLB structure for an XC3000 device.
Figure 1.1 XC3000 CLB Structure |  |
Each CLB includes two independent 4-input function generators (F and G) and two storage elements. A third function generator (H) can combine the outputs of F and G with a ninth input variable, thus making it capable of implementing some functions of up to nine variables. The function generators can also be configured as Read/Write memory or RAM.
The four control inputs, C1 through C4, can each generate any one of four logic signals used in the CLB. These control inputs can be used in any of three ways, as needed. These include: direct inputs to the two flip-flops, the clock enable to the two flip-flops, and the asynchronous control (direct Set or direct Reset) of the two flip-flops. In the XC4000X, CLB storage elements can also be configured as latches, with common clock and clock enable inputs.
Each CLB also includes dedicated high-speed carry logic that can generate the arithmetic carry output for incoming operands. The output can be passed to the adjacent upper or lower CLB function generator. (The upper CLB function generators are only used in the 4000 EX/XL devices.) This connection is independent of normal routing resources. Dedicated carry logic improves the performance of the arithmetic and counting functions.
The following figure shows the CLB structure for the XC4000.
Figure 1.2 XC4000 CLB Structure | |
The XC5200 CLB consists of four logic sections. Each logic section contains an independent 4-input function generator (F), a storage device (FD), and control logic. There are five independent inputs and three outputs to each logic cell.
The control logic provides direct access to the data input of the flip-flop through the direct input pin (DI). The control logic also consists of high-speed carry logic for fast implementation of arithmetic and counting functions. Furthermore, it can also be used as a cascade chain allowing high-speed pattern decode and other wide-logic functions.
The storage device in each logic cell is configurable as either a D flip-flop or a latch. The XC5200 CLB has 20 independent logical inputs, a clock, clock enable, and asynchronous clear. Each CLB also has 12 independent outputs that permit maximum utilization of the CLB resources.
The following figure shows the structure of the XC5200 CLB.
Figure 1.3 XC5200 CLB Structure | |
Each Virtex CLB has two independent fast carry logic chains. These chains allow two independent two-operand functions or one three-operand function to be placed in the device.
For more information about the Virtex series, see the Xilinx Programmable Logic Data Book, or refer to the Virtex web page at (http://www.xilinx.com/products/virtex.htm).
The Spartan series CLBs include three look-up tables (LUTs) which are used as logic function generators. There are also two flip-flops and two groups of signal steering multiplexers.
For more information about the Spartan series, see the Xilinx Programmable Logic Data Book, or refer to the Spartan web page at (http://www.xilinx.com/products/spartan.htm).
The structure of IOBs varies between architectures. Click the following desired architecture type for more information.
XC3000 IOB input includes both registered and direct input paths. Each output provides optional inversion, optional tristate control inversion, a controllable slew-rate, and a register. You can invert IOB clock pins on the same die edge. Configuration options on the inputs include a pull-up resistor. An example of IOB structure is shown in the following figure.
Figure 1.4 XC3000 IOB Structure | |
XC4000 IOB input includes both registered and direct input paths. Each output provides a tristate output buffer that can be driven by a registered or direct output signal. Configuration options on the IOB output include an inversion, a controllable slew-rate output, a tristate control inversion, a clock inversion, and programmable flip-flop initialization states. Configuration options on the inputs include clock inversion and a programmable delay to eliminate input hold time.
A pull-up or pull-down resistor can be activated for either inputs or outputs. Input registers can be flip-flops or latches with programmable initialization states.
The IOB structure for the XC4000E family is shown in the following two figures.
Figure 1.5 XC4000E IOB Structure | |
The following figure shows the structure of the XC4000X IOB.
Figure 1.6 XC4000X IOB Schematic | |
The IOB includes a direct input and a tristatable output. Configuration options on the IOB include input inversion, output inversion, tristate control inversion, a controllable slew-rate output, and a programmable delay to eliminate the input hold time when the input buffer directly sources a flip-flop. A pull-up or pull-down resistor can be activated for either inputs or outputs.
An updated schematic of the XC5200 IOB structure is in the Xilinx Programmable Logic Data Book.
User-configurable IOBs provide the interface between external package pins and the internal logic. Each IOB controls one package pin, and can be configured for input, output, or bidirectional signals.
For information about the Spartan device series IOB structure, refer to the Xilinx Programmable Logic Data Book.
External signals interface with the Virtex IOB, offering registered or direct paths to the internal CLBs. Input paths include an optional delay for accommodating varying setup and hold requirements. Outputs can be tri-stated with an optional register on the output enable path. The Virtex IOB can be configured to support many varying system standards, such as GTL and SSTL3. Refer to the Virtex Family datasheet for more details.
Each Xilinx FPGA device includes global resources, which distribute clock signals throughout the device with minimal skew.
The different types of FPGA routing resources are described in this section. Routing resources are used to connect the CLBs and IOBs on your device. The Xilinx mapping, placement, and routing software chooses the best resource to use for a particular signal type. For more detailed information about routing resources for each Xilinx FPGA, refer to The Programmable Logic Data Book.
Figure 1.7 Horizontal and Vertical Longlines (XC3000) | |
Figure 1.8 Example of CLBs with Direct Interconnect (XC3000) | |
Figure 1.9 General Purpose Interconnects (GPIs) | |
Figure 1.10 Programmable Interconnect Points (PIPs) | |
A matrix of switches is located at the intersections of the horizontal and vertical groups of general-purpose interconnect segments. These matrices are also referred to as magic boxes. Possible pin-to-pin connections for an XC3000 switching matrix are shown in the following figure.
Figure 1.11 Switching Matrix | |
