The Xilinx Development System documentation set consists of a series of books that help you to learn and use the Xilinx M1.5 software and CAE interface tools.
There are several different types of books included in the collection.
Known issues specifically related to CAE tool packages are included in the release document for that tool package.
Click the following appropriate book title to read a description of each manual provided with the Xilinx Development System.
There are separate book collections for the Alliance and Foundation Software Series; each collection contains appropriate manuals from the following list.
An asterisk “*” next to the book title indicates that it is a printed book. The Quick Start Guide for both Alliance and Foundation Software is delivered in printed and online formats.
The CPLD Schematic and Synthesis Design Guides (which include updated flowcharts of the design process) can be ordered from the Xilinx customer service department.
The following sections briefly describe the information contained in each manual.
The Alliance Quick Start Guide provides an overview of the features and additions to Xilinx's newest product software. This book details how to use the M1.5 software, and includes sections detailing CAE interface setup for use with Xilinx devices.
The Foundation Quick Start Guide provides an overview of the features and additions to Xilinx's newest Foundation software. The primary focus of this guide is to show the relationship between the design entry tools and the design implementation tools.
This guide contains information you need during the FPGA development process. It contains an overview of the design entry, design implementation, and design verification process, for device configuration. This book focuses on the Xilinx Alliance M1.5 Software.
The Foundation Series User Guide provides a detailed description of the Foundation design methodologies, design entry tools, and both function and timing simulation. The manual also briefly discusses the Xilinx Design Implementation Tools.
This manual describes the Xilinx hardware components and associated software interfaces. The hardware includes FPGA and CPLD demonstration boards, which are used for design verification, and various download cables. The book also provides detailed connection and configuration information for the hardware.
The Constraints Editor User Guide describes the Xilinx graphical user interface (GUI) that can be used after running the NGDBuild program to modify or delete existing constraints or add new constraints to a design.
This guide explains how to use the Cadence Concept schematic editor with the Xilinx software. The guide also explains how to generate a symbol/body for LogiBLOX modules within Concept, how to convert Concept Verilog output files to EDIF files with CONCEPT2XIL, and how to conduct functional and timing simulations.
This guide explains how to use the Mentor Graphics interface software with Xilinx software. There is also information on using the Mentor Graphics Design Manager interface, which is configured for the design, simulation, and implementation of Xilinx Programmable Logic Devices (PLDs).
This book explains how to use the Viewlogic interface software to translate your FPGA or CPLD designs from Viewlogic schematics to implemented design and simulation files.
This manual describes the Xilinx Synopsys Interface (XSI)program, a tool that allows you to implement Field Programmable Gate Array (FPGA) designs using either the Synopsys FPGA Compiler or Design Compiler synthesis tools.
This book describes individual components of the Xilinx Development System software, which includes programs to generate EDIF files and BIT files used primarily for FPGA architectures. The book covers all the program options, syntax, and input and output files that are generated by these programs.
This manual shows how to use the Xilinx Foundation Express program to translate and optimize a Verilog HDL description into an internal gate-level equivalent.
This manual shows how to use the Xilinx Foundation Express program to compile VHDL designs.
This book describes Xilinx's JTAG Programmer software, a tool used for In-system programming. You can use this software in conjunction with download cables for downloading, reading back, and verifying design configuration data. The book also describes how perform functional tests of your devices and how to probe internal logic states of a CPLD design.
This manual describes the Design Manager, a tool for managing multiple implementations of the same design. This manual also explains the Flow Engine, which implements designs and explains how to interact with other programs that run in the Design Manager environment. These programs include the Design Editor, the Timing Analyzer, the Hardware Debugger, the PROM File Formatter, and the PROM Programmer.
The EPIC Design Editor Reference/User Guide describes the functions of EPIC (Editor for Programmable ICs), which is a low level graphical editor program. EPIC enables you to place and route critical components before running automatic place and route tools on an entire design. You can also modify placement and routing manually, interact with the physical constraints file (PCF) to create and modify constraints, and verify timing against constraints using this program.
The LogiBLOX Reference/User Guide describes the LogiBLOX (blocks of logic optimized for Xilinx™) synthesis tool, which consists of a library of modules you can use to describe a system by means of high-level functions instead of gate-level primitives. This book also explains how to use the LogiBLOX program to create designs.
This manual describes how to use the Xilinx Floorplanner, a graphically based tool that allows you to interactively and automatically place logic symbols from a hierarchical design into a Xilinx target FPGA.
This manual describes how to program, verify, and debug FPGA devices. It describes the XChecker cable and explains how to connect the cable pins to your target device for various functions: downloading, verification, and debugging.
This manual describes Xilinx's Timing Analyzer program, a graphical user interface tool that performs static analysis of a mapped FPGA or CPLD design. The mapped design can be partially or completely placed, routed, or both.
This manual explains how to use the PROM File Formatter graphical interface tool. This program allows you to format bitstream files into HEX format files which are compatible with Xilinx and third-party PROM programmers. You can use the PROM files to program a PROM device, which is then used to configure daisy chains of one or more FPGAs for one application (configuration) or several applications (reconfiguration).
This book describes the components or macros that you use to create your designs as well as the attributes and constraints used to process your design during logic implementation. The Libraries Guide also discusses relationally placed macros (RPMs). These macros contain relative location constraints (RLOC) information. The Xilinx unified libraries enable you to convert designs easily from one device family to another.
This manual provides a general overview of designing Field Programmable Gate Arrays (FPGAs) using Hardware Description Languages (HDLs). It includes design hints for both novice and experienced HDL users who are designing FPGAs for the first time.
This manual provides a general overview of designing Field Programmable Gate Arrays (FPGAs) using Hardware Description Languages (HDLs). It includes design hints for both novice and experienced HDL users who are designing FPGAs for the first time. The examples in this manual are written specifically for Synopsys compilers.
This guide covers design techniques for schematic entry tools. It also includes information to embed behavioral modules and migrate designs between different families.
This book provides information on using the CPLD fitter and supported CAE interfaces to create schematic-based designs for Xilinx CPLD devices. It focuses on schematic design techniques, including using library components in schematics.
This guide describes the CPLD synthesis design process when using the Xilinx Synopsys Interface (XSI) with the Xilinx XC7000 and XC9000 device families. This includes an overview of Synopsys setup file preparation, installation verification, and a design walk through for implementing these designs in the workstation environment.
This document describes how to install the Alliance Software for both PC and UNIX platforms. The book also includes instructions for installing and operating the DynaText® book collection browser, as well as a list of known software issues and workarounds at the time of the release.
This document describes how to install the Xilinx Foundation Series Software. The book also includes instructions for installing and operating the DynaText book collection browser, as well as a list of known software issues and workarounds at the time of the release.
Xilinx offers several other methods of learning the software tools and finding the latest design information.
Xilinx provides the Answers book as an online document. This book contains a comprehensive list and complete description of Known Issues for the 1.5 software.
Xilinx has developed platform-specific tutorials that walk you step by step through the major functions of your CAE design tools, such as schematic capture and functional and timing simulation. The tutorials may also include information on design issues specific to your platform.
Updated tutorials will be available after June 30, 1998 from the Xilinx web site and on the AppLINX CD. The web site location is (http://www.xilinx.com/support/techsup/tutorials). Please contact your local Sales Representative for a copy of the AppLINX CD.
Online help is available for some Xilinx software products. It includes procedures, definitions, command information, reference material, error messages, and basic information on the product. It includes context-sensitive help.
Consult The Programmable Logic Data Book for device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging. This document is available in hard copy and on the Xilinx web site (http://www.xilinx.com). See (http://www.xilinx.com/partinfo/databook.htm) for the current version of this book.
