Design simulation involves testing your design using software models. It is most effective when testing the functionality of your design and its performance under worst-case conditions. You can easily probe internal nodes to check your circuit's behavior, and then use these results to make changes in your schematic.
Simulation is performed using third-party tools that are linked to the Xilinx Development System. Use the various CAE-specific interface user guides, which cover the commands and features of the Xilinx-supported simulators, as your primary reference.
The software models provided for your simulation tools are designed to perform detailed characterization of your design. You can perform functional or timing simulation, as described in the following sections.
Functional simulation determines if the logic in your design is correct before you implement it in a device.
Functional simulation can take place at the earliest stages of the design flow. Since timing information for the implemented design is not available at this stage, the simulator tests the logic in the design using unit delays.
It is usually faster and easier to correct design errors if you perform functional simulation early in the design flow.
The “Three Verification Methods of the Design Flow” figure shows the design flows for integrated and non-integrated simulation tools. Integrated tools such as Mentor or Viewlogic contain a built-in interface which links the simulator and a schematic editor, allowing the tools to use the same netlist. You can move directly from entry to simulation when using a set of integrated tools.
Functional simulation in schematic-based tools is usually performed immediately after Design Entry in the capture environment. The schematic capture tool requires a Xilinx Unified Library and the simulator requires a library if the tools are not integrated. Most of the schematic-based tools will require translation from their native database to XNF or EDIF for implementation. The return path from implementation is usually XNF or EDIF with certain exceptions where a schematic tool is tied to an HDL simulator.
Timing simulation verifies that your design runs at the desired speed for your device under worst-case conditions. This process is performed after your design is mapped, and placed and routed. At this time, all design delays are known.
The “Design Verification Flow, Gate Level Simulation” figure outlines how to perform timing simulation once delay information is available after placement and routing. Timing simulation is valuable because it can verify timing relationships and determine the critical paths for the design under worst-case conditions. It can also determine whether or not the design contains set-up or hold violations.
Figure 4.4 Design Verification Flow, Gate Level Simulation |  |
The NGD2XNF program (and the XNF output file format) are not supported in the M1.5 software.
To input timing information into your design, you must convert the routed NCD file into an NGA file. The resulting NGA file can then be translated by NGD2EDIF, NGD2VER, or XNF2NGD. These netlist writers create suitable formats for various simulators.
Naming the nets during your design entry is very important for both functional and timing simulation. This allows you to find the nets in the simulations more easily than looking for a machine-generated name.
