Pre-Simulation Translation

Before simulation occurs, the physical design information must be translated and distributed back to the logical design. This back-annotation process is done with a program called NGDAnno. NGDAnno creates a database for the netlist writers, which translate the back-annotated information into a netlist format that can be used for simulation. The back-annotation flow is shown in the following figure.

Figure 4.3 Back-Annotation

NOTE

The NGD2XNF program (and the XNF output file format) are not supported in the M1.5 software.

This section describes the NGDAnno program and the supported netlist writers in more detail. This information is included in the following sections.

• NGDAnno
  
  
• Netlist Writers
  
  
• Invoking Translation Programs
  
  
• Additional Translation Options
  
  

NGDAnno

NGDAnno is a program that distributes delays, setup and hold time, and pulse widths found in the physical NCD design file back to the logical NGD file.

NGDAnno merges mapping information from the NGM file with placement, routing, and timing information from the NCD file. THis data is combined into a generic annotated (NGA) file. The NGA file is input to the appropriate netlist writer (NGD2EDIF, NGD2VER, or NGD2VHDL) which then converts the binary Xilinx database format back to an ASCII netlist.

NOTE

Use caution when making changes to the functional behavior of your design. For example, if you make logical changes to an NCD design from within EPIC, the graphical design editor, NGDAnno will be unable to correlate the changed objects in the physical design with the objects in the logical design. It will then recreate the entire NGA design from the NCD and issue a warning indicating that the NCD is out of sync with the NGM.

An NCD file is input to the NGDAnno program. The NCD file can be a mapped-only design, or a partial or fully placed and routed design. An NGM file which is created by the mapper is an optional source of input.

The output of NGDAnno is an NGA file, which is a back-annotated NGD file. For details on NGDAnno refer to the “NGDAnno” chapter of the Development System Reference Guide.

Netlist Writers

Netlist writers take the output of NGDAnno and create a simulation netlist in the specified format. An NGD or NGA file is input to each of the netlist writers. The NGD file is a logical design file containing primitive components, while the NGA file is a back-annotated logical design file. Following is a list of the supported M1 netlist writers with descriptions of their input and output files.

• NGD2EDIF - takes an NGD or NGA file and translates it into an EDIF netlist.
  
  Output from the NGD2EDIF program is an EDN file, a netlist in EDIF format. The default EDN file produced by NGD2EDIF is generic. If you want to produce EDIF targeted to Mentor Graphics or Viewlogic, you must include the -v (vendor) option. For details on commands and options, see the Development System Reference Guide.
  
  
• NGD2VER - translates an NGD or NGA file into a Verilog netlist (V) file. If the input is an NGA file, NGD2VER will also generate an SDF (Standard Delay Format) file.
  
  The resulting V and SDF files will have the same root name as the NGD or NGA file unless you specify otherwise.
  
  The SDF file contains timing information intended solely for use with the Verilog file which was generated from the same NGA file. Do not attempt to use the SDF file in conjunction with the original Verilog netlist design or the product of another netlist writer.
  
  
• NGD2VHDL - translates an NGD or NGA file into a VHDL netlist (VHD). If the input file is an NGA file, NGD2VHDL will also generate an SDF (Standard Delay Format) file. The VHD and SDF files will have a tim_sim root name by default. To change the root name of your files, go to the “Simulation Data Options” dialog box and select the “VHDL/Verilog” tab.
  
  

For more information on the Netlist Writers or NGDAnno, refer to the Development System Reference Guide.

Invoking Translation Programs

You can invoke any of the supported netlist programs from the UNIX or DOS command line. Most of the programs can be invoked from the Design Manager.

Select the NGD2 and netlist writer commands as follows.

1. Open the Xilinx Design Manager
   
   
2. In the “Implementation Options” dialog box, select the “Simulation Data Options” tab.
   
   
3. In the “General” Field, select your desired netlist writer.
   
   

The post NGDBuild and post-MAP translations can only be invoked from the Unix^™ or Dos^™ command line. You cannot interrupt the design flow of the Design Manager for outputting at intermediate stages.

Additional Translation Options

In addition to back-annotating a fully routed design, you can also back-annotate a translated but unmapped design and a mapped but unrouted design. You can also create an output netlist to allow simulation of the design at the different stages of development in the Xilinx environment.

Pre-MAP Circuit Verification

For example, if you want to verify that the circuit logic is correct before you map, place, and route the design, you can use the data in an unmapped NGD design as input to the netlist writers NGD2EDIF, NGD2VER, or NGD2VHDL. You then run a simulation program on the resulting netlist.

Simulating Designs with Block Delays

To simulate a design that contains only IOB and CLB block delays, you can take the NCD file produced by MAP and then run NGDAnno. Afterwards, run the appropriate netlist writer to generate a simulatable netlist.

Block delays are generally 50% of your path delay. Simulating with block delays is an imprecise method of determining whether your timing will be met before you actually place and route. (However, this simulation type is less time consuming than performing a full timing simulation.) The simulation process is shown in the “Back-Annotation” figure.