This appendix contains definitions and explanations for terms used in the EPIC manual.
Attributes are instructions placed on symbols or nets in an FPGA or CPLD schematic to indicate their placement, implementation, naming, directionality, or other properties.
The automatic placement (AutoPlace) is software that selects sites intelligently based on routability. You can automatically place selected components in your design.
AutoRoute automatically routes the objects you specify.
A bank shot is a way of indirectly connecting two switch box pins that cannot be connected directly. If you want to route a bank shot through a switch box, you must select (in the correct order) the local lines leading to all of the pins you want to connect.
A group consisting of one or more logic functions.
Carry logic is special interconnect that speeds up the carry path of adders and counters from one CLB to another. This dedicated carry line runs along each column of CLBs as well as the top and bottom CLBs.
The CLB, or Configurable Logic Block, constitutes the basic FPGA cell. It consists of two 16-bit function generators (F or G), one 8-bit function generator (H), two registers (flip-flops or latches), and reprogrammable routing controls (multiplexors).
Rather than using pull-down menus or push buttons, you can enter commands in the Command Line dialog box. The Command Line dialog box does not appear automatically when you start EPIC.
A component is an instantiation of a physical logic cell such as a CLB or IOB.
Constraints are specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints.
Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. PAR does not attempt to change the location of constrained logic.
CLBs are arranged in columns and rows on the FPGA device. The goal is to place logic in columns on the device to attain the best possible placement from the point of view of performance and space.
A constraints file specifies constraints (location and path delay) information in a textual form. You can also place constraints on a schematic.
This tool calculates and displays the delay associated with load pins and driver pins in a given net or path.
Design Mode is where you create a new design file or edit an existing one.
Physical DRC is a series of tests to discover physical errors and some logic errors in your design.
A device is an integrated circuit or other solid-state circuit formed in semiconducting materials during manufacturing.
You can control the display objects in the editing area. You can turn off the display of individual object layers, such as switches, wires, and routed connections, to make your design easier to edit. The editing area displays a graphical representation of the interior of the FPGA device.
Allows you to view the logic in a programmable block. You can edit the logic if you are in Read/Write mode.
The Editor for Programmable Integrated Circuits (EPIC) is a graphical application for displaying and configuring Field Programmable Gate Arrays (FPGAs).
Script that determines what EPIC commands are performed when EPIC starts up.
File used to determined the items in EPIC's menu bar and the contents of each of the menu bar's pull-down menus.
You can customize the epic.ini initialization file by creating an epicuser.ini file in your home directory. When EPIC is initialized, it reads the epic.ini file first and then the epicuser.ini file.
The EPL file is a command log file. This file records all EPIC commands executed and output generated. Use this file to recover an aborted EPIC session.
A macro pin used to connect the components in an instantiated macro to other components in your design (outside of the macro).
An FPGA, or field programmable gate array, is a class of integrated circuits pioneered by Xilinx for which the logic function is defined by the customer using Xilinx development system software after the IC has been manufactured and delivered to the end user.
Highlights selected objects by changing their color.
The history area is located below the editing area. It displays commands and responses. Commands entered in the Command Line dialog box are scrolled in the history area and executed. All error messages, warnings, and command responses are written into the history area.
The history area allows you to scroll back through the last N lines of text. The history area displays commands and responses.
An IOB is a collection or grouping of basic elements that implement the input and output functions of an FPGA device.
An EPIC layer contains all of one type of object (for example, all long lines in the device, or all components in the design database).
The Layer Visibility dialog box allows you to specify which objects are displayed in the editing area. Select the layers you want displayed and deselect the layers you want hidden. Select the Apply button to activate your selections.
The List dialog box displays a list of the components, nets, layers, paths, and macros in your design.
Local lines usually span across multiple CLBs; typically they are between switch boxes. Local lines do not directly connect to site pins, such as direct connects, and they do not span across the entire length of the device, such as long lines.
The locator area is used in the EPIC window to pan to a selected area. The locator area is displayed in the upper right corner of the EPIC window. This area shows the location of the editing area relative to the area of the entire device. As you pan and zoom the editing area, notice the corresponding changes in the size and position of the rectangle within the locator area.
Lock placement applies a constraint to all placed components in your design. This option specifies that placed components cannot be unplaced, moved, or deleted.
The logic block editor allows you to edit the internal logic of a selected programmable component. Use the Edit Block to start the logic block editor.
A long line connects to a primary global net or to any secondary global net. Each CLB has four dedicated vertical longlines. These lines are very fast. Long lines usually span the entire width or height of the device.
A look-up table, or LUT, implements Boolean functions.
See the “Physical Macros” section.
A copy of a macro library file inserted in a design file. When you add a macro instance to a design you “instantiate” the macro. A design may contain multiple instances of the same library file, and each will receive a unique name. Since the library file is copied into the design file when you instantiate a macro, if you then change the library file the changes will not be reflected in the macro instantiated in the design file. In this User's Guide, the word “macro” may be used instead of “macro instance.” A macro library file will always be referred to as a “macro library file.”
A file containing the definition of a macro. Macro library files, which have an .nmc extension, are created and edited in EPIC, operating in macro mode.
EPIC is in macro mode when you are creating or editing a macro library file.
The menu bar is the area located at the top of the main window that provides access to the menus. Refer to the “Menu Commands” chapter for information on the menu commands.
Mapping is the process of assigning a design's logic elements to the specific physical elements that actually implement logic functions in a device.
A NCD file is the output design file from the MAP program and represents the physical design.
1. A net is a logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
2. A net is an electronic connection between components or nets. It can also be a connection from a single component. It is the same as a wire or a signal.
Displays the delay for all pins in a net. You can either find the delay for all pins in the net or you find delays for specific pins.
A NMC file contains a physical macro which can be created or viewed with EPIC.
A package is the physical packaging of a chip, for example, PG84, VQ100, and PC48.
A path is a connected series of nets and logic elements. A path has a start point and an end point that are different depending on the type of path. The time taken for a signal to propagate through a path is referred to as the path delay.
A path delay is the time taken for a signal to propagate through a path.
The PCF file is an ASCII file containing physical constraints created by the MAP program as well as physical constraints entered by you. You can edit the PCF file in EPIC.
Physical Design Rule Check (DRC) is a series of tests to discover logical and physical errors in the design. Physical DRC is applied to EPIC and BITGEN. Results of the DRC are written into the history area.
A physical macro is a logical function that has been created from components of a specific device family. Physical macros are stored in files with the extension .nmc. A physical macro can be created or viewed when EPIC is in macro mode.
A pin is an attachment point on a site or a component. Nets can be attached to pins.
Pinwires are wires which are directly tied to the pin of a site (i.e. CLB, IOB, etc.)
Placing is the process of assigning physical device cell locations to the logic in a design.
The push button panel provides a convenient way to perform frequently used commands. The push button panel is located on the right side of the editing area.
A ratsnest consists of lines that are point to point connections between unrouted pins on a given net.
A component in the macro library file used as a reference when a macro instance is placed, moved, or copied. Placement and routing of all other pre-placed macro components are determined relative to this component.
The router is the utility that connects all appropriate pins to create the design's nets.
The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.
A route that can pass through an occupied or an unoccupied CLB site is called a route-through. You can manually do a route-through in EPIC. Route-throughs provide you with routing resources that would otherwise be unavailable.
A site is a programmable logic element (used or unused) location within the device, sites are potential locations for components and are displayed in the editing area as outlines of components.
Speed is a function of net types, CLB density, switching matrices, and architecture.
A switch matrix is a collection of transistors located between CLB blocks that enables the connection of two interconnect lines. PPR uses the switch matrices and interconnects to connect CLB inputs and outputs. Switch matrices reduce some of the net delay. They have three possible directions: top, bottom, and left.
Timing is the process that calculates the delays associated with each of the routed nets in the design.
TRACE (Timing Reporter and Circuit Evaluator) is a program you can run within EPIC that provides static timing analysis of the physical design based on input timing constraints.
A wire is a net or a signal. See the “Net” section.
