Input/Output modules represent the physical pins on a device that are actually used in a design. Pad modules are connected to the I/O modules to simulate input/output wires.
There are three types of I/O modules. These modules represent all the possible logic combinations that can fit into the Input/Output blocks (IOBs).
Input ModulesInput modules are device-input modules that connect a Pad to an internal pin signal or bus.
Figure 4.12 The Input Module |  |
Output modules are device-output modules that connect an internal pin signal or bus to a Pad.
Figure 4.13 The Output Module | |
Bi-directional modules combine the function of an Input module with that of an Output module.
Figure 4.14 The Bi-directional I/O Module | |
I/O modules can be registered or buffered. Buffered I/O modules simply output whatever appears on the input port. Registered I/O modules are used to store the I/O values and are implemented as IOB registers.
Bi-directional modules expand into one or more input and output data and control signals, plus tristate input/output buffers.
This section describes the input pins of the Input and Output modules. The input pins of the Bi-directional module are just combinations of the same input pins for the Input and Output modules.
The P pin represents the input to the Input module
Connections: This input is always specified. For Bi-directional modules, P is both the input and output of the I/O module. Connect a Pad module to the P pin to simulate a wire.
If you select an input operation that includes a register, the following inputs are also available.
Figure 4.15 Registered Input Module | |
The Clock input loads the selected data into the register on the rising (positive) edge. You can implement an active falling (negative) edge by connecting an inverter to the Clock input.
Connections: The Input Clock pin is always specified on registered modules. If the Clock Enable input is specified and Low, the Clock is temporarily disabled and the register contents remain unchanged.
Input Clock Enable (ICLK_EN)When it is specified and Low, the Input Clock Enable input temporarily disables the clock, causing the register to hold its previous value. When the Input Clock Enable input is High, the input data is loaded into the register on the next active Clock transition.
Connections: The Input Clock Enable pin is optional. If this input is not specified, the Clock is always enabled.
The O pin is the input to the Output module.
Connections: The O pin is always connected.
If you select an output operation that includes a register or tristate, the following pins are available.
Figure 4.16 Registered Output Module With Tristate | |
The Output Enable input appears on a buffered tristate Output module. For all devices except the XC9500 and XC9500XL families, when Output Enable is High, the signal on the P pin is tristated. When Output Enable is Low, the signal is enabled. For the XC9500 device family, the signal on the P pin is tristated when Output Enable is Low and enabled when Output Enable is High. For the XC9500XL family, the value of the OE Phase attribute determines the behavior of the signal on the P pin when Output Enable is High or Low.
Connections: The Output Enable pin is always specified on a tristate Output module.
In the Unified Libraries this pin is labeled T (for Tristate) rather than OE on the output buffers. Also, the bubble is not present, indicating that the signal is active when T is High.
The Clock pin, when enabled, loads the selected data into the register on the rising edge. You can use an active falling edge by connecting an inverter to the Clock input.
Connections: The Output Clock pin is always specified on a registered Output module.
Output Clock Enable (OCLK_EN)When the Clock Enable pin is High, the input data is loaded into the register on the next active Clock transition. When the Clock Enable is Low, the register contents are unaffected by the active Clock transition (hold).
Connections: The Clock Enable pin is optional. If this pin is not specified, the Clock is always enabled.
This section describes the output pins of the Input and Output modules. The output pins of the Bi-directional module are just combinations of the same output pins for the Input and Output modules.
The I pin is the output of the buffered Input module.
Connections: The I pin is always connected.
On a registered module, the I pin is replaced by the IQ pin.
On a registered buffer Input module, the output of the register is the IQ pin and the buffer output is the I pin.
Connections: The IQ pin is always specified in a registered Input module.
The P pin represents the output of the Output module and connects to a signal outside the chip.
Connections: This pin is always specified. You must connect a Pad symbol to the P pin of an Output module.
The IO Type attribute specifies the type of I/O function: Input, Output, or Bi-directional.
Usage: For each mode you select, the Input/Output module graphic is adjusted appropriately. Refer to the appropriate pin descriptions section.
Input Operation (IN_TYPE)The Input Operation attribute specifies the operation mode of the Input module.
Usage: Valid values include Buffer Only, Register Only, Latch Only, Buffer and Register, and Buffer and Latch.
If you select an input option with a register, the Input Clock pin is automatically added. The Input Clock Enable pin is optional.
If you select an input option with a latch, the Input Gate pin is automatically added. The Input Gate Enable pin is optional.
Output Operation (OUT_TYPE)The Output Operation attribute specifies the operation mode of the Output module.
Usage: Valid values include Buffer Only, Register Only, Tristate, and Register with Tristate.
If you select an output option with a register, the Output Clock pin is automatically added. The Output Clock Enable pin is optional.
If you select an output option with a tristate, the Output Enable pin is automatically added.
Async. Val (ASYNC_VAL)The Asynchronous Value attribute controls the power-on state of the registers.
Usage: This attribute applies to the registered I/O modules only. For dual-register modules, you can specify the asynchronous value for either or both registers by using any of the following formats:
IN:15
OUT:31
OUT:31.IN:15
where OUT is the Output register and IN is the Input register.
OE Phase (OE_PHASE)This attribute determines whether the signal on the P pin in a tristate Output module is tristated when the Output Enable is High or Low.
Usage: This attribute can only be set by the user for the XC9500XL device family. The attribute is set to Active High for the XC9500 family and to Active Low for all other families by default.
