The Memory module allows you to create ROM, RAM, Synchronous RAM, and Dual Port RAM modules. These modules store information in the form of words in a tabular fashion. Use these modules for the following purposes.
Figure 4.17 The Memory Module |  |
The Read-Only Memory (ROM) module is a memory for storing information from a user-edited memory file (.mem file). The word storage capacity of the ROM is called the depth. The depth must be a multiple of 16, ranging from 16 to 256 words.
The size of the data stored within the ROM ranges from 1 through 64 bits. The largest word stored in the ROM should be within the boundaries set by the bus width of the Data Out pin, DO.
To read a word from the ROM, specify a binary number on the Address bus that matches the location of the desired word. The data is immediately output at the Data Out pin. Only addressable locations that are within the valid range will be synthesized.
Figure 4.18 The ROM Module Symbol | |
A binary value on the Address port selects a word by pointing to the ROM location in which that word is stored. The Data Output port displays the selected word.
Connections: The Address input is always specified.
The Data Output port reflects the word currently addressed in the ROM.
Connections: The Data Output pin is always specified.
The Depth attribute defines the number of locations that can be addressed in the ROM module or the number of words that can be stored in the ROM. The depth must be a multiple of 16 and range from 16 to 256 words.
Mem File (MEMFILE)The Memory File attribute references the name of a memory definition file that defines the contents of the ROM. The name of the memory definition file must have a .mem file extension. The extension can be omitted from the Memfile attribute. If the memory definition file exists, it will be read; otherwise, you can generate a Memfile template file from LogiBLOX by clicking on the Edit button. The template file created by LogiBLOX does not contain correct data and must be edited before you can use it. Refer to the “Memory Definition File Syntax” section for more information.
Usage: The Memory File attribute must be specified for ROM modules.
Multiplexer Style (STYLE)The Multiplexer Style attribute determines the way multiplexers are built in memory modules. These multiplexers use address lines as select lines and choose among the outputs of the memory distributed in the CLBs. The Wired AND style uses Tristate buffers and long lines. The Normal Gates style uses CLB logic functions to implement the multiplexers.
Usage: Choose between the Maximum Speed, Normal Gates, and Wired AND values. If Memory Depth is set less than 64, the Maximum Speed value defaults to Normal Gates. If Memory Depth is set to 64 or more, Maximum Speed defaults to Wired AND.
Use RPMs (USE_RPM)The Use RPMs attribute determines whether the function generators that comprise the ROM maintain a constant relative location to each other. This attribute applies to the XC4000 and XC5200 device families only.
Usage: Use RPMs can be set to True or False. The default is False.
Trim (TRIM)Empty data columns are preserved by the software unless the Trim attribute is set to TRUE. If the software trims empty ROM primitives, it may yield a smaller design. The trade-off of having a smaller design is that you may not modify the contents of the ROM without rerouting the design. The default value is FALSE.
Random-Access Memory modules are used to store dynamic data. There are three different types of RAM modules: level-sensitive Asynchronous RAMs, Synchronous RAMs, and Dual Port RAMs.
RAM modules are not supported for the XC3000, XC5200, and XC9500 device families.
There are two ways of using RAM modules. One way consists of storing data dynamically by addressing locations from the Address bus pin and writing binary data furnished by the Data Input port into these locations. The other way consists of initializing the RAM module's contents at power-up by specifying the Memfile attribute. You can access the latter information the same way as you would in a ROM module. Furthermore, you can overwrite the information by writing new data in the RAM locations.
To store a new word into the RAM and read it out on the output port, the address of the location to be written is placed on the address bus pin (A), the data to be written is placed on the data bus pin (DI), and Write Enable is driven from low to high.
For Asynchronous RAM modules, when Write Enable goes High, the data on the Data Input port is immediately stored into the currently addressed location and read out at the Data Out port. For Synchronous RAM and Dual Port RAM modules, the Write Enable Clock must also go High. Once a word is stored in the RAM, you can re-access it from the Address pin independently of the Write Enable signal.
If Write Enable stays Low while a value appears at the Data In port, this data is ignored. Only values that occur on a rising Write Enable pulse can be written. The data on the Address bus and on the Data Input port cannot change for the duration of the Write Enable pulse.
In XC4000 devices, the contents of the RAM module are undefined at power-up. In XC4000E and XC4000EX devices, the power-on state of the RAM can be controlled by using a Memory Definition File (.mem file).
You can use the RAM module like a ROM to store a memory definition file that fits the depth of the module. The depth of the module refers to the word storage capacity of the RAM. The depth must be a multiple of 16, ranging from 16 to 256 words.
The width of the words contained in the memory definition file must also be within the width of the RAM module. The width of the RAM module ranges from 1 through 64 bits. The width of the module is set by the bus width of the Data Out pin.
You may overwrite the RAM locations using the Data Input pin to feed new data into the locations addressed by the Address bus.
Figure 4.19 The RAM Module Symbol | |
Each time the Write Enable pin goes High, the data on the Data Input is stored into the addressed RAM location when Write Enable is active High. In addition, to prevent new data from overwriting the current location, there is a time frame during which the data on the Address and the Data In pins cannot change: when the Write Enable pin is Low before going High and triggering a write operation, and when the Write Enable goes Low again immediately after going High. These states are referred to as the Setup and Hold times respectively. The setup and hold time constraints on the Address and Data Input pins with respect to the Write Enable pulse cause the Level-Sensitive RAM module to have lower bandwidth than the synchronous RAM modules.
Figure 4.20 The Synchronous RAM Module Symbol | |
This module is identical to the Level-Sensitive RAM except that writes to the RAM are synchronized to the Write Enable Clock. When the Write Enable input is high and the Write Enable Clock goes from low to high, the data on the Data Input pin is written to the location specified by the Address input pin. The data on the Data Input pin appears on the Data Output pin after it is written to the RAM. New data appearing in the Data Input pin must wait for the next high on the Write Enable pin and a low to high transition on the Write Enable Clock before it is written.
This module is faster than a Level-Sensitive RAM due to the synchronous nature of the write, which allows pipelining of data on the Data Input pin.
Figure 4.21 The Dual Port RAM Module Symbol | |
The Dual Port RAM module includes two independent pairs of Address and Data Output pins that share access to the same region of memory, allowing simultaneous read and write access to it. Writes are synchronized by the Write Enable Clock input.
All input pins of the respective RAM modules are always specified.
DIThe Data Input port determines the contents as well as the data that appears at the Data Output port that will be stored into the RAM when the Write Enable input goes High. Only the data currently at the Data Input port is read when Write Enable goes High.
Connections: The Data Input port is always specified.
WR_ENFor Asynchronous RAM modules, when the Write Enable input is High, the data on the Data Input port is written into the currently selected address location. When Write Enable is Low, no new data can be written into the RAM. For Sync_RAM and DP_RAM modules, a High on this input must be accompanied by a rising edge of the Write Enable Clock input to store the data into the memory location.
Connections: Write Enable is always specified.
WR_CLKWhen the Write Enable Clock input goes High, the data on the Data Input port is stored into the currently addressed location and immediately read out at the Data Output port.
Connections: This input is available and required for the SYNC_RAM and DP_RAM modules only. For a valid write operation, the Write Enable input must first go High before this input goes High.
AThis input bus addresses a location in the RAM. Its purpose is twofold: 1) it selects the location whose contents are to appear on the Data Output port, or 2) it selects the location where new data is written whenever the Write Enable input goes High (for the level-sensitive RAM) or when the Write Enable Clock goes high while the Write Enable input is High (for SYNC_RAM and DP_RAM). The width of the Address port is always log2 Depth.
Connections: The Address input is always specified.
DPRAThe Dual Port Read Address port is used for the secondary address line in a dual port RAM.
Connections: The Dual Port Read Address input is available for Dual Port RAM modules only. It is always specified.
The Data Output port displays the contents of the location being accessed. The width of the Data Output port is set by the Bus Width attribute.
Connections: The Data Output pin is always specified. On DP_RAM modules this output port is called Single Port Output.
SPOThe Single Port Output is used to output the data that appears on the Data Input pin whenever the Write Enable Clock is High.
Connections: This output is only used by DP_RAM modules. It is always specified.
DPOThe Dual Port Output is used to output the data that resides at the address specified by the Dual Port Read Address (DPRA) input of the DP_RAM module. The value of DPO can change independently of the Write Enable Clock going High.
Connections: This output is used only by DP_RAM modules. It is always specified.
The Depth attribute defines the number of words that can be stored in the RAM module. The depth must be a multiple of 16 and range from 16 to 256 words. The default value is 16. The width of the address port is always log2 Depth.
Mem File (MEMFILE)The Memory File attribute references the name of a Memory Definition File that defines the contents of the RAM. The name of the Memory Definition File must have a .mem file extension. The extension can be omitted when specifying the Memfile attribute. If the Memory Definition File exists, it will be read; otherwise, you can generate a template file from LogiBLOX by clicking on the Edit button. The template file created by LogiBLOX does not contain valid data and must be edited before you can use it.
Usage: The Memory File attribute is optional for RAM modules.
Multiplexer Style (STYLE)The Multiplexer Style attribute determines the way multiplexers are built in memory modules. These multiplexers use address lines as select lines and choose among the outputs of the memory distributed in the CLBs. The Wired AND style uses Tristate buffers and long lines. The Normal Gates style uses CLB logic functions to implement the multiplexers.
Usage: Choose between the Maximum Speed, Normal Gates, and Wired AND values. If Memory Depth is set less than 64, the Maximum Speed value defaults to Normal Gates. If Memory Depth is set to 64 or more, Maximum Speed defaults to Wired AND.
Use RPMs (USE_RPM)The Use RPMs attribute determines whether the function generators that make up the RAM maintain a constant relative location to each other. This attribute applies to the XC4000 and XC5200 device families only.
Usage: Use RPMs can be set to True or False. The default is False.
A memory definition file, or MEMFILE, consists of two parts - the Header, which describes characteristics of the ROM or RAM module, and the Data portion, which defines the contents of the memory module. The beginning of the Data portion of the file is delimited by the DATA keyword. The memory definition file is not case-sensitive.
The Header defines characteristics of the memory module, such as its size and radix. Each of the following keywords must exist on a single line in the MEMFILE. Continuation characters are not allowed in the Header.
Depth (optional)The Depth attribute defines the depth, in words, of the module. The Depth is specified in decimal notation, unless a radix definition precedes it. The value specified must match the value of the Memory Depth attribute.
depth memory_depth
Width (optional)The Width definition sets the width of the memory, which is the number of bits in each word. The width must be a positive, non-zero, integer. The Width is specified in decimal, unless a radix definition precedes it. The value specified must match the value of the Bus Width attribute.
width memory_width
DefaultThe Default definition sets the value of all memory locations that are not specified in the MEMFILE Data section. If no default value is specified, all unspecified locations are set to zero. The default definition uses the current radix, which is 10, unless a radix definition precedes it.
RadixThis keyword defines the radix (or base) of the numbers following each radix definition in the MEMFILE. Multiple radix definitions can appear in the header and affect all non-radixed numbers up to and including the next Radix definition. A radix definition affects the MEMFILE Header section and the MEMFILE Data section.
The default radix for the MEMFILE Header section is 10. The default radix for the MEMFILE Data section is 16.
radix integer
CommentsComments must be preceded by a semicolon. You can start your comment anywhere on the line. A semicolon at the end of a line generates a blank comment because it does not affect the next line of text.
; commentstring
ExampleThe following example illustrates the syntactical concepts defined above:
; The default radix is 10
Default 10; Defines the default ROM contents = 1010=10
Radix 16; Re-defines the default radix = 1610=16
Depth 10; Defines the depth = 1016=16
Radix 10; Re-defines the default radix = 1016=16
Width 12; Defines the width = 1216=18The data values specified in the MEMFILE Data Section define the contents of the memory. Data values are specified sequentially, beginning with the lowest address in the memory, as defined. The address of a data value may be specified. The default radix of the data values is 16. If more than one radix definition is given in the MEMFILE Header Section, then the last such definition is the radix used in the Data Section.
data data values
Data values may be separated by commas, white space, or both.
AddressingAn address is specified as follows.
address:
For example, the following definition defines a 16-word memory with the contents 6, 4, 5, 5, 2, 7, 5, 3, 5, 5, 5, 5, 5, 5, 5, 5, starting at address 0. Note that the contents of locations 2, 3, 6, and 8 through 15 are defined via the default definition. Two starting addresses, 4 and 7, are given.
depth 16
default 5
data 6,4,
4: 2, 7,
7: 3You can specify ASCII data values by enclosing a string of characters in double quotes. You can include a double quote by prefacing the character with a backslash (\). A MEMFILE may contain both ASCII strings and numeric values. Each ASCII character gets assigned to one address location.
For instance, the following defines the contents of 16 memory locations. Two ASCII BEL characters (7) are defined here - one before the “R” and one after the two “l” characters.
data 7, "Ring the bell", 7, 0.
LogiBLOX imposes some restrictions on the memfiles that were previously supported by Memgen or X-BLOX 5.2.1:
