CC8CE, CC16CE

8-, 16-Bit Cascadable Binary Counters with Clock Enable and Asynchronous Clear

CC8CE and CC16CE are, respectively, 8- and 16-bit (stage), asynchronous, clearable, cascadable binary counters. These counters are implemented using carry logic with relative location constraints to ensure efficient placement of logic. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TC output is High when all Q outputs are High.

Larger counters are created by connecting the count enable out (CEO) output of the first stage to the CE input of the next stage and connecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. The clock period must be greater than n(t_CE-TC), where n is the number of stages and the time t_CE-TC is the CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CE input; use the TC output if it does not.

The counter is asynchronously cleared, with Low outputs, when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs			Outputs
CLR	CE	C	Qz - Q0	TC	CEO
1	X	X	0	0	0
0	0	X	No Chg	No Chg	0
0	1		Inc	TC	CEO
z = 7 for CC8CE; z = 15 for CC16CE TC = Qz•Q(z-1)•Q(z-2)•...•Q0 CEO = TC•CE

Topology for XC4000 and Spartans

This is the CC8CE (8-bit) and CC16CE (16-bit) topology for XC4000 and Spartan series devices.

Topology for XC5200

This is the CC8CE (8-bit) and CC16CE (16-bit) topology for XC5200 devices.

Figure 4.18 CC8CE Implementation XC4000, Spartans

Figure 4.19 CC8CE Implementation XC5200

Figure 4.20 CC8CE Implementation Virtex