FJKRSE
J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Virtex
|
|---|
Macro
| Macro
| Macro
| Macro
| Macro
| Macro
| Macro
| Macro
|
FJKRSE is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). When synchronous reset (R) is High, all other inputs are ignored and output Q is reset Low. (Reset has precedence over Set.) When synchronous set (S) is High and R is Low, output Q is set High. When R and S are Low and CE is High, output Q responds to the state of the J and K inputs, according to the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
R
| S
| CE
| J
| K
| C
| Q
|
|---|
1
| X
| X
| X
| X
| 
| 0
|
0
| 1
| X
| X
| X
|
| 1
|
0
| 0
| 0
| X
| X
| X
| No Chg
|
0
| 0
| 1
| 0
| 0
| X
| No Chg
|
0
| 0
| 1
| 0
| 1
|
| 0
|
0
| 0
| 1
| 1
| 0
|
| 1
|
0
| 0
| 1
| 1
| 1
|
| Toggle
|
