FJKSRE
J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Virtex
|
|---|
Macro
| Macro
| Macro
| Macro
| Macro
| Macro
| Macro
| Macro
|
FJKSRE is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset (R), and clock enable (CE) inputs and data output (Q). When synchronous set (S) is High, all other inputs are ignored and output Q is set High. (Set has precedence over Reset.) When synchronous reset (R) is High and S is Low, output Q is reset Low. When S and R are Low and CE is High, output Q responds to the state of the J and K inputs, as shown in the following truth table, during the Low-to-High clock (C) transition. When CE is Low, clock transitions are ignored.
The flip-flop is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
S
| R
| CE
| J
| K
| C
| Q
|
|---|
1
| X
| X
| X
| X
| 
| 1
|
0
| 1
| X
| X
| X
|
| 0
|
0
| 0
| 0
| X
| X
| X
| No Chg
|
0
| 0
| 1
| 0
| 0
| X
| No Chg
|
0
| 0
| 1
| 0
| 1
|
| 0
|
0
| 0
| 1
| 1
| 0
|
| 1
|
0
| 0
| 1
| 1
| 1
|
| Toggle
|
