| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Virtex |
|---|---|---|---|---|---|---|---|
| N/A | Primitive | Primitive | N/A | N/A | Primitive | Primitive | Macro |
ILDX_1 is a transparent data latch, which can be used to hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously cleared with Low output, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.
For information on legal IFDX, IFDX_1, ILDX, and ILDX_1 combinations, refer to the “ILDX, 4, 8, 16” section.
| Inputs | Outputs | ||
|---|---|---|---|
| GE | G | D | Q |
| 0 | X | X | No Chg |
| 1 | 1 | X | No Chg |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 |  | D | d |
| d = state of input one setup time prior to Low-to-High gate transition | |||
Figure 6.39 ILDX_1 Implementation Virtex |  |
