LD
Transparent Data Latch
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Virtex
|
|---|
N/A
| N/A
| Macro
| Macro
| Macro
| N/A
| Macro
| Primitive
|
LD is a transparent data latch. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is High. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains Low.
The latch is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR (XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.
Refer to the “LD4, 8, 16” section for information on multiple transparent data latches for the XC4000X, XC9000, and SpartanXL.
Inputs
| Outputs
|
|---|
G
| D
| Q
|
|---|
1
| 0
| 0
|
1
| 1
| 1
|
0
| X
| No Chg
|
| D
| d
|
d = state of input one setup time prior to High-to-Low gate transition
|
