LD_1

Transparent Data Latch with Inverted Gate

LD_1 is a transparent data latch with an inverted gate. The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is Low. The data on the D input during the Low-to-High gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains High.

The latch is asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR (XC5200) and GSR (XC4000X, SpartanXL, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP or STARTUP_VIRTEX symbol.

Inputs		Outputs
G	D	Q
0	0	0
0	1	1
1	X	No Chg
	D	d
d = state of input one setup time prior to Low-to-High gate transition

Figure 7.4 LD_1 Implementation XC4000X, SpartanXL

Figure 7.5 LD_1 Implementation XC5200