Attributes are used to control how the software uses the architecture specific features of CPLDs. See the device data sheets for more information about these device features.
This appendix contains the following sections:
Instantiated attributes are applied by instantiating the following components in your design and connecting them to the affected signal.
This attribute inhibits the software from optimizing the logic that drives the signal passing through the KEEP cell.
To specify that a signal is to remain as a macrocell output, use:
U1: KEEP port map (O=>outgoing_signal, I=>incoming_signal);
The following attributes can be specified in the Synopsys dc_shell for Xilinx CPLD designs. See the Synopsys Design Compiler manual for more information on using the set_attribute and set_pad_type commands.
The dc_shell set_pad_type command with parameter -exact explicitly controls allocation of global input buffers. The format is:
set_pad_type -exact buffer_type port_name
where buffer_type is one of BUFG, BUFGTS, or BUFGSR.
The dc_shell set_pad_type command with parameter -exact BUFG is used to explicitly control the use of global clock pins, and reference an input port of your design. For example:
set_pad_type -exact BUFG clock1
If you need to explicitly control the use of global 3-state control pins, you can specify the set_pad_type command in your dc_shell script with the parameter -exact BUFGTS, and reference an input port of your design. For example:
set_pad_type -exact BUFGTS enable1
If you need to explicitly control the use of the global set/reset pin, you can specify the set_pad_type command in your dc_shell script with the parameter -exact BUFGSR and reference an input port of your design. For example:
set_pad_type -exact BUFGSR reset1
The cell names BUFG, BUFGTS, and BUFGSR must be upper case.
The set_pad_type command must be invoked before the insert_pads command.
As an alternative, you can use a UCF file to apply the BUFG property to an ordinary input port after synthesis. The UCF file syntax is:
NET port_name BUFG=buffer_type;
where buffer_type is one of CLK(for BUFG), OE(for BUFGTS), or SR(for BUFGSR).
The set_pad_type -slewrate command controls the output buffer slew rate.
The format is:
set_pad_type -slewrate slew_value port_list
where slew_value is either HIGH (for slow slew rate) or NONE (for fast slew rate), and port_list is either one or more output port names or the keyword all_outputs().
By default, the slew rate of all the output buffers (OBUF, OBUFE and IOBUFE) is controlled by the fitter options (default fast). However, in order to reduce possible noise problems, it is recommended that you use the fast transition default only for those output signals that require maximum speed.
To set all outputs to slow slew rate, use the following command:
set_pad_type -slewrate HIGH all_outputs ()
After you have globally changed all outputs to the HIGH option (for slow signal transition) you can set any individual output for fast signal transition by using the following command:
set_pad_type -slewrate NONE port_name
The set_pad_type command must be invoked before the insert_pads command.
As an alternative, you can use a UCF file to apply the FAST or SLOW property to an ordinary output port where no slewrate was set using the set_pad_type command during synthesis. The UCF file syntax is:
NET port_name FAST;
or
NET port_name SLOW;
The LOC attribute is used to specify the pins on which to place output signals.
The format is:
set_attribute port_name LOC pin_number -type string
where:
For example, for PC and PQ packages:
set_attribute RDY LOC p23 -type string
For example, for PG and BG packages:
set_attribute RDY LOC K13 -type string
The pin assignment attribute overrides previously saved pinouts when running cpld with the -pinlock option.
NET port_name LOC=pin_number;
for instance,
NET ABC LOC=P12;
The LOC attribute can also be used to specify the function block or macrocell number into which a node is to be mapped. Function block assignment may be useful to take advantage of the high-speed local feedback paths of XC9500 devices.The syntax is:
set_attribute node_name loc FBnn -type string
or
set_attribute node_name loc FBnn_mm -type string
where node_name is the name of the signal net appearing at the output of a CPLD macrocell (or the cell driving that signal), nn is a legal function block number for the target device, and mm is a legal macrocell number within the function block.
NET node_name LOC=FBnn[mm];
The init attribute is used to specify the initial (power up) state of registers in your design.
The syntax is:
set_attribute register_name init state -type string
where:
For example:
set_attribute “QOUT<2>_reg” init S -type string
NET net_name INIT=state;
or
INST inst_name INIT=state;
The pwr_mode attribute can be used to select the power consumption (standard or low-power) of specific macrocells in the design. The syntax is:
set_attribute node_name pwr_mode mode -type string
where node_name is the name of a signal (net) appearing at the output of a CPLD macrocell (or the cell that drives the signal), and mode is either std (standard) or low.
If the logic driving the named signal is collapsed by the fitter, the pwr_mode attribute will be ignored.
NET node_name PWR_MODE= mode;
The following dc_shell timing constraints are available:
You can use the following command to declare a clock input port and place a timing specification on the specified clock net. The register-to-register delays between all flip-flops on the named clock will be constrained by the specified period.
The create_clock command creates a cycle time specification on the specified clock signal as follows:
create_clock clock_port -period delay
where clock_port is the name of the clock input port and delay is the clock cycle time in nanoseconds.
The Synopsys max_period command is not supported by the Xilinx fitter; use the create_clock command instead.
NET clock_port TNM=clock_port;
TIMESPEC TSid=PERIOD:clock_port:delay;
The set_max_delay command specifies delay constraints for specific paths originating from input (or I/O) ports or flip-flop cells and terminating at output (or I/O) ports or flip-flop cells. The syntax of the set_max_delay command is:
set_max_delay delay -from source -to destination
For example, to specify the propagation delay from the CLEAR input port to the DONE output port:
set_max_delay 20 -from CLEAR -to DONE
| Source | Destination | Affected Timing Path |
|---|---|---|
| input or I/O port (except clock) | output or I/O port | pad-to-pad propagation delay |
| input or I/O port (except clock) | register cell | register setup time from specified port(s) with respect to flip-flop's clock pin. |
| register cell | register cell | register-to-register delay (cycle time), regardless of each register's clock source (overrides create_clock period constraint covering same registers |
| register cell | output or I/O port | register clock-to-output delay from flip-flop's clock pin to output pad. |
| clock input port | output or I/O port | register clock-to-output delay from the specified clock input to specified output port |
| clock input port | register cell | not used for CPLD designs |
TIMESPEC TSid=FROM:source:TO:destination:delay;
The set_output_delay command establishes clock-to-output delay specifications based on values specified in the create_clock or set_max_delay constraints or creates tighter constraints for named output ports as follows:
set_output_delay delay -clock clock output_port
When the named output ports are driven by registers covered by a create_clock period constraint, the set_output_delay constraint specifies how much time (delay) before the next clock edge the named outputs need to become stable.
In this case, the set_output_delay constraint specifies the delay path between the clock input pin of the CPLD device and the named output pin(s) according to the following relationship:
set_output_delay_value = create_clock_period_value - cpld_clock_to_output_delay
where set_output_delay_value is the delay value specified in the set_output_delay constraint, create_clock_period_value is the period value specified in a previous create_clock constraint, and cpld_clock_to_output_delay is the desired worst-case propagation delay between the clock input pin and output pin(s) of the CPLD.
This command also changes the values of pad-to-pad or clock-to-output delay specifications created by the set_max_delay command, by making the constraints tighter by the amount specified by the delay value for the named outputs.
When using the set_output_delay constraint, the named clock must be explicitly declared as a global clock input port by using the set_pad_type -exact BUFG command.
NET output_port OFFSET=OUT:delay:BEFORE:clock;
The set_input_delay command establishes register setup time specifications based on create_clock or set_max_delay commands or creates tighter constraints on named input ports as follows:
set_input_delay delay -clock clock input_port
When the named input ports feed into registers covered by a create_clock period constraint, the set_input_delay constraint specifies how much time (delay) after the previous clock edge the named inputs are expected to become stable.
In this case, the set_input_delay constraint specifies the setup time requirements between data input pin(s) and the clock input pin of the CPLD device according to the following relationship:
set_input_delay_value = create_clock_period_value - cpld_external_setup_time
where set_input_delay_value is the delay value specified in the set_input_delay constraint, create_clock_period_value is the period value specified in a previous create_clock constraint, and cpld_external_setup_time is the desired worst case setup time between the data input pin(s) and the clock input pin of the CPLD.
This command also changes the values of pad-to-pad delay or register setup time specifications created by the set_max_delay command, by making the constraints tighter by the amount specified by the delay value for the named inputs.
When using the set_input_delay constraint, the named clock must be explicitly declared as a global clock input port by using the set_pad_type -exact BUFG command as described in the section Special I/O Ports in chaper 2.
NET input_port OFFSET=IN:delay:AFTER:clock;
