CPLD Synthesis Design Guide

Preface

About This Manual

This manual has been created to provide guidance in use of Synthesis Design for XC9500 and XC9500XL CPLDs in the workstation environment. Practical examples in this manual apply to the Synopsys compiler and simulator.

Manual Contents

This manual covers the following topics.

• “Getting Started with Synopsys for CPLDs” chapter. This chapter shows you how to prepare your setup files and verify your installation. It also provides a design walk-through as an overview of the basic steps for implementing Xilinx XC9000 CPLD designs using Synopsys.
  
  
• “Designing with CPLDs” chapter. This chapter discusses how to use design techniques, library cells and cpld command parameters to get the best performance from Xilinx XC9000 CPLDs.
  
  
• “Compiling and Fitting a CPLD Design” chapter. This chapter describes how to compile your design using the Synopsys Design Compiler shell (DC Shell).
  
  

• “Simulating Your Design” chapter. The Xilinx CPLD Synopsys Interface supports both functional and timing simulation of VHDL designs using the VSS simulator. This chapter shows you how to prepare designs for simulation and how to use a test bench.
  
  
• “Library Component Specifications” appendix lists library components used in CPLD designs.
  
  
• “Attributes” appendix lists attributes used in CPLD designs.
  
  
• “Fitter Command and Option Summary” appendix lists fitter options entered from the Design Manager, and lists fitter options entered on the cpld command line.
  
  

Conventions

This manual uses the following conventions. An example illustrates each convention.

• Courier font indicates messages, prompts, and program files that the system displays.
  
  speed grade: -100
  
  
• Courier bold indicates literal commands that you enter in a syntactical statement.
  
  rpt_del_net=
  
  Courier bold also indicates commands that you select from a menu.
  
  File Open
  
  
• Italic font denotes the following items.
  
  
  • Variables in a syntax statement for which you must supply values
    
    edif2ngd design_name
    
    
  • References to other manuals
    
    See the Development System Reference Guide for more information.
    
    
  • Emphasis in text
    
    If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
    
    
• Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.
  
  edif2ngd [option_name] design_name
  
  Square brackets also enclose footnotes in tables that are printed out as hardcopy in DynaText^®.
  
  
• Braces “{ }” enclose a list of items from which you choose one or more.
  
  lowpwr ={on|off}
  
  
• A vertical bar “|” separates items in a list of choices.
  
  symbol editor_name [bus|pins]
  
  
• A vertical ellipsis indicates repetitive material that has been omitted.
  
  IOB #1: Name = QOUT'
  IOB #2: Name = CLKIN'
  .
  .
  .
  
  
• A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.
  
  allow block block_name loc1 loc2 ... locn;
  
  

In addition, Xilinx has created several conventions for use within the DynaText online documents.

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