This section shows you how to declare the initial states of registers in your design for simulation. If your design does not depend on the initial states of any registers, then you can skip this section and go to the next section, "Creating a Test Bench File".
The actual initial states of your registers are determined by the initial state attributes specified in DC Shell during compilation. By default, all registers initialize to zero in CPLD designs.
The timing simulation model produced by the Xilinx software reflects the actual register initial states that are implemented in the device.
All registers in Xilinx CPLDs are initialized when power is applied. You must perform the necessary steps to initialize the registers in your design at beginning of timing simulation for consistent simulation results.
The following sections show you how to set up your design to perform register initialization for both functional and timing simulation.
When you generate your timing simulation model, ngd2vhdl or Simulation Output Options on the Design Manager automatically create a new signal in the model that you can stimulate in your test bench at the beginning of the simulation waveform to simulate power-on. For CPLD designs an internal net named PRLD is normally created. If you want to make the XC9000 PRLD signal accessible to a VHDL test bench, you can specify the ngd2vhdl -gp option to create a port named PRLD.
When simulating, you must first pulse PRLD high, prior to exercising the logic, to get all the registers into their initial states. If you used the ngd2vhdl -gp option to create a PRLD port for your XC9000 design simulation, you must list PRLD in the port list of the CPLD in your test bench.
The PRLD signal is used for timing simulation only; it is not used for functional simulation and it cannot be used in your design. However, if you include it in your functional simulation test bench, that test bench can also be used later for timing simulation without modification.
If you include the PRLD signal in your test bench file for functional and timing simulation, you must also include PRLD in your port declarations in your source design file as follows:
port (... PRLD : in std_logic ...);
PRLD is not used anywhere else in your design. It will be ignored during synthesis; you will get warnings about the unconnected port during the Compile and Insert_pads operations. The Xilinx fitter software will also discard the unconnected port during implementation.
If the behavior of your CPLD design does not depend on the power-up state of any register, you do not need to use the ndg2vhdl -gp option and you do not need to pulse the PRLD net during simulation.
Simulate register initialization by defining, in your VHDL source design file, the initial values for registered signals. Use signal declarations such as the following:
port signal_name: port_direction signal_type := initial_value;
signal signal_name: signal_type := initial_value;
variable signal_name: signal_type := initial_value;
For example:
port Nreg5: out std_logic := '0';
signal Qreg6: std_logic := '1';
variable Qreg: std_logic_vector := "00000001";
These initial values are used only for functional simulation; they are not used during synthesis and the compiler will give you a warning that these values are being ignored. Also, these initial values are not used by the Xilinx software for device implementation because the initial values from these declarations are not written into the netlist.
You are now ready to create a test bench file.
