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Creating a Test Bench File

This section shows you how to create a test bench file that can be used for both functional and timing simulation. The example test bench presented here consists of a VHDL file containing one instance of a CPLD design being tested and a procedure that applies simulation input waveforms to the CPLD.

Initializing Registers

If you are using the -gp option, prepare your test bench to pulse the appropriate initialization port.

In the test bench, include the PRLD input port in the CPLD component declaration and in its instance port map as shown in the following section. At the beginning of the simulation sequence, apply an active-high pulse to the PRLD port to initialize the registers during timing simulation. The pulse is ignored during functional simulation because the PRLD signal is not used anywhere in the source design. For functional simulation, all registers are initialized before the first simulation cycle (at time zero) by the initial values declared in your source design file.

If you are simulating a CPLD design using Verilog, pulse the internal PRLD net high at the beginning of simulation to initialize your registers.

Configuration Declaration

For any design or test bench you wish to simulate using VSS, you must declare a configuration which identifies the specific architecture you are applying to a design. When you invoke the VSS simulator, you must select the name of a configuration that has been previously analyzed.

The following example shows a typical configuration declaration in a VHDL test bench file for a CPLD design for which the ngd2vhdl -gp option has been enabled. If the test bench is always used to simulate the design source file, the design does not need its own configuration declaration.

entity scan_tb is 
   end scan_tb;                                     --test bench has no ports--
 
 architecture test of scan_tb is 
        component scan 
             port (CLOCK, CLEAR, ...                --same as in scan.vhd-- 
                  PRLD : in std_logic); 
        end component; 
        signal CLOCK, CLEAR, ...PRLD;               --same as ports of scan.vhd-- 
   begin 
        UUT: scan port map (CLOCK, CLEAR, ... PRLD);--connect local signals to ports--
        driver: process begin 
             PRLD <= '1';CLEAR <='0';...            --assert initial values on all 
						      inp ports-- 
             wait for 25ns;                         --wait, -- 
             PRLD <= '0';...                        --release PRLD before applying 
                                                      other input transitions-- 
             wait;                                  --after all inputs, suspend 
						      process-- 
      end process; 
 end test; 
 configuration CFG_SCAN_TB of scan_tb is 
           for test 
                end for; 
   end CFG_SCAN_TB;

After you have created a test bench file, you are ready to begin using a VSS simulator (such as vhdldbx) for functional simulation.

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