A symbol is a graphic representation of a level of hierarchy. Symbols can represent user-defined macros or design files from other sources. This section describes how to create a symbol.
The File Open dialog box closes and a symbol window opens.
The symbol window contains a box called a block sheet that defines the perimeter of the symbol. The block sheet does not show up on the screen when the symbol is placed in a design schematic. You can see only the elements that you add to the symbol.
The initial size of the symbol, shown as the area defined by the block sheet, is 1 inch by 1 inch or 100 x 100 grid units. For most symbols, you must enlarge or reduce this default size.
To change the size of the symbol, follow these instructions.
Figure 3.10 Symbol Properties Dialog Box |
Most symbols have a visible frame or symbol body to which pins attached. To add a box for a symbol, follow these steps.
You can move the mouse in any direction, as long as you go from corner to opposite corner. The symbol appears similar to the one represented in the following figure.
Figure 3.11 Symbol Box |
A two-pip distance exists from the symbol box to the edge of the work area. While not required, this distance provides a constant symbol pin length. The Xilinx Unified Libraries follow this convention.
To add pins to the symbol, follow these steps.
Pin labels must exactly match the labels used for the same signals in the corresponding schematic. For example, for a pin labeled clock on the symbol, there must exist a net labeled clock in the symbol's underlying schematic. To add pin labels, follow the procedure given in the Adding Labels section in this chapter.
You can attach attributes to pins as well as to symbols. The most common attribute applied to a pin is the PINTYPE attribute. The valid optional values for the PINTYPE attribute are IN, OUT, and BI. You can add attributes to pins using the procedure given in the Adding Attributes section in this chapter.
You can enter part of your design in some form other than schematics, such as state machine entry. You can also bring in netlist files produced by interface software from a Xilinx Alliance partner. Whatever the form of entry, you must use as the starting point for inclusion into a Viewlogic schematic design a Xilinx Netlist Format (XNF) file or an EDIF 2 0 0 netlist file. This file must reside in the project directory. Without an XNF file, you cannot include this portion of the design; with it, the origin of the logic becomes irrelevant.
See the Design and Simulation Techniques chapter for instructions about creating custom symbols for non-schematic-based modules.