Labeling identifies a net, bus, component, or pin by assigning a text string to it. Bus labels are required, and labeling all nets on the schematic makes debugging easier. Label all user-created macros.
Follow the conventions described in this section when you add labels.
FPGA names for nets, buses, components, and pins must follow these conventions.
You cannot apply the physical names associated with every resource on every part to signals and symbols. These reserved names include CLBs, IOBs, clock buffers, BUFTs, oscillators, package pin names, CCLK, DP, GND, VCC, RT, PWRDN, and RST. Other examples include CLB names such as AA and AB, pin names such as P1 and P2, pad names such as PAD1 and PAD2, and primitive names such as TDO, BSCAN, M0, M1, M2, or STARTUP.
ViewDraw and ViewSim fully specify hierarchical signal names; some examples follow.
As these examples clearly show, putting more labels in your design makes it easier to locate signals for simulation.
To give components more meaningful names than those issued by ViewDraw, use the Label field to name symbols, just as you would nets. The following lists some examples of symbol names.
Components with or without user-assigned labels receive names in the following manner.
top-level_instance\instance
For example, $1I3\$1I5 represents a component (instance I5) located one level below symbol $1I3.
To ensure that bus signals process correctly, use the following naming conventions.
You must consistently apply the order of bus indices for a single bus. For example, do not connect busa[0:3] to busb[3:0] at another level of your schematic unless you are deliberately reversing the bus order.
See the following table for examples of legal bus names.
Bus Name | Description |
---|---|
Q[0:7] | 8-bit bus, signals Q0 (MSB) through Q7 (LSB) |
Q[7:0] | 8-bit bus, signals Q7 (MSB) through Q0 (LSB) |
Q[7:0],SET,CLK | 10-bit bus, signals Q7 through Q0; also signals SET and CLK |
A[7:0],B[7:0] | 16-bit bus, signals A7 through A0 and signals B7 through B0 |
DATA[0:7:2] | 4-bit bus, signals DATA0, DATA2, DATA4, and DATA6 |
DATA[0:F/H] | 16-bit bus, specified in hexadecimal (You can also specify a bus in decimal, octal, or binary.) |
Follow these steps to add a label to a net, bus, component, or pin.
Figure 3.12 Net Properties Dialog Box |
You must label all buses and nets going into a bus. See the Net Names section, Component Names section, and Bus Names section earlier in this chapter for information on how to label these entities correctly.
To invoke the Net Properties dialog box, double-click on the net or bus. Use the Net Properties dialog to change some of the local properties of nets or buses, including the following.
Under the Attributes tab, you can add or modify net and bus attributes. To change the visibility of an attribute, select the attribute, then change the Visibility field. Click OK to save the change. See the Adding Attributes section of this chapter for more information.
Access other properties through the Label Properties dialog box. To invoke this dialog box, double click on the label (make sure the net or bus itself is not selected). In addition to the Label, Visibility, Color, and Sense parameters, you can modify the following.
Under the Color, Etc. tab, choose the color and Font for this label.
To apply any changes made in the Net Properties or Label Properties dialog boxes, click on OK. To exit the dialog box without making schematic changes, click on Cancel.
You can set the default value of many of these properties from the Project Settings menu selection.