At this point in the tutorial, you created or edited the following four schematic files: CALC, ALU, ANDBLK2, and ORBLK2. You can use the design, at this point, only in an XC4000E device because these devices have several advanced features not found in other Xilinx device families. Two of these advanced features are the on-chip memory built into the XC4000E CLB and wide-edge decoders.
The RAM stack implements using a 16x4 RAM macro from the XC4000E library. Although the stack is 4x4, RAM and ROM are only available in 16x1 or 32x1 increments. This means the design uses only one fourth of the memory addresses. You can implement a stack four times as deep while still using only two CLBs. An equivalent flip-flop implementation requires 64 flip-flops or 32 CLBs. In this case, with a stack only four words deep, using the static memory feature of the XC4000E CLB still reduces the stack from eight CLBs to two CLBs.
To view the XC4000E stack implementation, follow these steps.
The schematic for RAM16X4S appears in the following figure.
Figure 8.40 RAM16X4S, XC4000E Implementation |
The device-independent stack implements by replacing the RAM16X4S with a register file that emulates a synchronous RAM with a set of flip-flops and multiplexers. Use this implementation for any Xilinx device, even one from the XC4000E family.
If targeting an XC4000E device, you can skip this section to take advantage of the RAM feature of the XC4000E.
Make the stack a device-independent schematic as follows.
Figure 8.41 Replace Instance Dialog Box |
You can use the RAM4_9K component only in an XC9500 design, as the aliases in the macro refer to that family library.
If targeting the Calc design to an XC9500 or other device outside the XC4000 family, you must also remove the CLOCKGEN circuitry, which includes the OSC4 component. Replace it with an external source.
Because a pad now sources the CLK signal, it must generate externally.
Figure 8.42 Device-Independent Clock Source |