Using LogiBLOX

LogiBLOX allows you to quickly synthesize modules for common functions such as adders, counters, and multiplexers. It allows you to create components of arbitrary bus width (for example, a 17-bit adder) and automatically uses the best architectural resources for a particular target device family. In this optional section, you replace the ADSU4 component in the ALU schematic with a LogiBLOX adder. If you choose to leave the ALU schematic in its original form, read this section but do not make save any changes.

Creating and Instantiating a LogiBLOX Module

To replace the ADSU4 symbol with a LogiBLOX module.

1. Bring the ALU schematic into view.
   
   
2. Select the ADSU4 component, then select Edit Delete to delete the symbol from the schematic.
   
   
3. Select Tools Add LogiBLOX from the menu bar. After loading, the Setup dialog box appears.
   
   
4. Under the Device Family tab, select xc4000e. Under the Options tab, verify the selection of “Gate Level EDIF model” and that “Behavioral VHDL model” is not selected. The VHDL model compiles more quickly, but requires an Extended Viewlogic package, because the VHDL model requires Speedwave, the Viewlogic VHDL simulator. The Gate Level EDIF model is available to all licenses, as it only requires ViewSim. See the figure that follows.
   
   

   Figure 8.43 LogiBLOX Options Dialog Box

5. Click on OK. The LogiBLOX Module Selector dialog box appears.
   
   
6. In the Module Name field, type addsub4 (the user-given component name for the new LogiBLOX-generated module).
   
   
7. In the Module Type field, use the pull-down tab to select Adders/Subtracters. The symbol updates to show this type of component. The Bus Width field shows 4.
   
   
8. Single-click with the left mouse button to place a check mark in the Carry Input, Carry Output, and Sum boxes. Deselect any other checkboxes. The LogiBLOX Module Selector dialog box appears like the one shown in the next figure.
   
   

   Figure 8.44 LogiBLOX Module Selector Dialog Box

9. Click on OK to create symbol and an EDIF model for this LogiBLOX component. This takes a few moments.
   
   
10. After creating the LogiBLOX symbol, place it in the space left by the ADSU4. Do not worry about lining up pins with nets right now.
    
    
11. Complete the schematic by connecting the existing nets and buses. Note that the locations of the pins differ with the LogiBLOX component. Additionally, data inputs and output are now bus-wide. Your schematic now appears like the one in the figure that follows.
    
    

    Figure 8.45 Completed ALU Schematic with LogiBLOX

12. Check and save the ALU schematic.