This appendix contains definitions and explanations for terms used in the Foundation Series User Guide.
ABEL is a high-level language (HDL) and compilation system produced by Data I/O Corporation.
In state machines, actions are HDL statements that are used to make assignments to output ports or internal signals. Actions can be executed at several points in a state diagram. The most commonly used actions are state actions and transition actions. State actions are executed when the machine is in the associated state. Transition actions are executed when the machine goes through the associated transition.
An Electronic Design Automation (EDA) vendor. Aldec provides the Foundation Project Manager, Schematic Editor, Logic Simulator, and HDL Editor.
Aliases, or signal groups, are useful for probing specific groups of nodes.
A process performed to check the syntax of an HDL file.
Architecture is the common logic structure of a family of programmable integrated circuits. The same architecture can be realized in different manufacturing processes. Examples of Xilinx architectures are the XC4000, Spartan, and XC9500 devices.
Attributes are instructions placed on symbols or nets in a schematic to indicate their placement, implementation, naming, direction, or other properties.
Using the minimum number of registers to encode a state machine is called binary, or maximal, encoding, because the registers are used to their maximum capacity. Each register represents one bit of a binary number.
The BitGen program produces a bitstream for Xilinx FPGA device configuration. The BitGen program displays as the Configure step within the Flow Engine.
Instantiation where the synthesizer is not given the architecture or modules.
A group consisting of one or more logic functions. Also called CLB.
A component is an instantiation or symbol reference from a library of logic elements that can be placed on a schematic.
If there is more than one transition leaving a state in a state machine, you must associate a condition with each transition. A condition is a Boolean expression.
Constraints are specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints.
Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. CLBs are arranged in columns and rows on the FPGA device. The goal is to place logic in columns on the device to attain the best possible placement from the standpoint of both performance and space.
A GUI tool that you can use to enter design constraints. In Foundation 1.5, there are two constraint editors. The Express Constraints Editor is integrated with the synthesis tools for pre-implementation optimization. It available only in the Foundation Express product configuration. The Xilinx Constraints Editor is integrated with the Design Implementation tools and available in all product configurations.
A constraints file specifies constraints (location and path delay) information in a textual form. An alternate method is to place constraints on a schematic.
A software tool for generating and delivering parameterizable cores optimized for FPGAs. Like LogiBLOX modules, cores are high-level modules.
Complex Programmable Logic Device (CPLD) is an erasable programmable logic device that can be programmed with a schematic or a behavioral design. CPLDs constitute a type of complex PLD based on EPROM or EEPROM technology. They are characterized by an architecture offering high speed, predictable timing, and simple software.
The basic CPLD cell is called a macrocell, which is the CPLD implementation of a CLB. It is composed of AND gate arrays and is surrounded by the interconnect area.
CPLDs consume more power than FPGA devices, are based on a different architecture, and are primarily used to support behavioral designs and to implement complex counters, complex state machines, arithmetic operations, wide inputs, and PAL crunchers.
The CPLD Fitter implements designs for the XC9500 devices.
The Foundation design entry tools consist of the Schematic Editor, HDL Editor, and State Editor. The tools can be accessed via the Design Entry button in the Project Manager's Flow tab. The optional Base Express and Foundation Express packages contain VHDL and Verilog design entry tools.
A set of tools that comprise the mainstream programs offered in the Xilinx design implementation tools. The tools include NGDBuild, MAP, PAR, NGDAnno, TRCE, all the NGD2 translator tools, BitGen, PROMGen, and EPIC.
Xilinx Foundation 1.4 graphical user interface for managing and implementing designs. In Foundation 1.4, the Design Manager is accessed by selecting the Implement M1 button from the Project Manager. (For Xilinx Foundation 1.5 series, the Project Manager replaces the Design Manager.)
The HDL process that combines the individual parts of a into a single design and then synthesizes the design.
The Editor for Programmable Integrated Circuits (EPIC) is a graphical application for displaying and configuring FPGAs. You can use EPIC to place and route critical components before running the automatic place and route tools on your designs.
Engine used to compile VHDL and Verilog code for the Base Express and Foundation Express products.
GUI available in the synthesis phase of Foundation Express containing spreadsheets used to define specific optimization requirements. See also Express Time Tracker.The Express Time Tracker is available at the end of the synthesis phase of Foundation Express. It contains spreadsheets detailing optimization results.
GUI available at the end of the synthesis phase of Foundation Express. It contains spreadsheets detailing optimization results.
Design Entry tool to create and edit state machine descriptions.
The fitter is the software that maps a PLD logic description into the target CPLD.
Floorplanning is the process of choosing the best grouping and connectivity of logic in a design.
It is also the process of manually placing blocks of logic in an FPGA where the goal is to increase density, routability, or performance.
Field Programmable Gate Array (FPGA), is a class of integrated circuits pioneered by Xilinx in which the logic function is defined by the customer using Xilinx development system software after the IC has been manufactured and delivered to the end user. Gate arrays are another type of IC whose logic is defined during the manufacturing process. Xilinx supplies RAM-based FPGA devices.
FPGA applications include fast counters, fast pipelined designs, register intensive designs, and battery powered multi-level logic.
Finite State Machine.
A process to test the logic in a design before implementation to determine if it works properly. Uses unit delays because timing information is not available before implementation.
Guided design is the use of a previously implemented version of a file for design mapping, placement, and routing. Guided design allows logic to be modified or added to a design while preserving the layout and performance that have been previously achieved.
An existing NCD file is used to “guide” the current MAP run. The guide file may be used at any stage of implementation: unplaced or placed, unrouted or routed. In Foundation Series 1.5, guided mapping is supported through the standalone Design Manager.
Hardware Description Language. A language that describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog.
Design entry tool to produce/edit HDL files. The HDL Editor also provides a syntax checker, language templates, and access to the synthesis tools.
An HDL Flow project can contain VHDL, Verilog, or schematic top-level designs. It can contain underlying schematic, HDL (VHDL or Verilog), or State Machine designs. The entire design is always exported in HDL terms and synthesized. Top level schematic designs in an HDL Flow are exported as schematic netlists, optimized by the synthesis tool, and then exported for Implementation. On the Project Manager Flow tab, a Synthesis button is included between the Design Entry and Implementation buttons for this project type.
A design has a hierarchical structure if any of its components are instantiated as HDLs, schematics, netlists, LogiBLOX modules, or state machines.
A phase in the design process during which the design is placed and routed.
Incorporating a macro or module into a top-level design. The instantiated module can be a LogiBLOX module, VHDL module, Verilog module, schematic module, state machine, or netlist.
The Language Assistant in the HDL Editor provides templates to aid you in common VHDL and Verilog constructs, common logic functions, and architecture-specific features.
Lock placement applies a constraint to all placed components in your design. This option specifies that placed components cannot be unplaced, moved, or deleted.
A Xilinx design tool for creating high-level modules such as counters, shift registers, RAM, and multiplexers.The modules are customizable and pre-optimized for Xilinx FPGA and CPLD architectural features. All Xilinx devices with the exception of Virtex support LogiBLOX.
Logic is one of the three major classes of ICs in most digital electronic systems - microprocessors, memory, and logic. Logic is used for data manipulation and control functions that require higher speed than a microprocessor can provide.
The Library Manager is the tool used to perform a variety of operations on the design entry tools libraries and their contents. These libraries contain the primitives and macros that you use to build your design.
The Logic Simulator, a real-time interactive design tool, can be used for both functional and timing simulation of designs. The Logic Simulator creates an electronic breadboard of your design directly from your design's netlist. The Logic Simulator can be accessed by clicking the Functional Simulation icon on the Simulation button or the Timing Simulation icon on the Verification button in the Project Manager.
A macro is a component made of nets and primitives (flip-flops or latches) that implements high-level functions, such as adders, subtractors, and dividers. Soft macros and RPMs are types of macros.
A macro can be unplaced, partially placed, or fully placed, and it can also be unrouted, partially routed, or fully routed. See also “physical macro.”
The MAP program maps a logical design to a Xilinx FPGA. The input to a mapping program is an NGD file. The MAP program is initiated within the Flow Engine during Implementation.
Mapping is the process of assigning a design's logic elements to the specific physical elements that actually implement logic functions in a device.
An MRP (mapping report) file is an output of the MAP run. It is an ASCII file containing information about the MAP run. The information in this file contains DRC warnings and messages, mapper warnings and messages, design information, schematic attributes, removed logic, expanded logic, signal cross references, symbol cross references, physical design errors and warnings, and a design summary.
An NCD (netlist circuit description) file is the output design file from the MAP program, LCA2NCD, PAR, or EPIC. It is a flat physical design database correlated to the physical side of the NGD in order to provide coupling back to the user's original design. The NCD file is an input file to MAP, PAR, TRCE, BitGen, and NGDAnno.
A netlist is a text description of the circuit connectivity. It is basically a list of connectors, a list of instances, and, for each instance, a list of the signals connected to the instance terminals. In addition, the netlist contains attribute information.
The NGDAnno program distributes delays, setup and hold time, and pulse widths found in the physical NCD design file back to the logical NGD file. NGDAnno merges mapping information from the NGM file, and timing information from the NCD file and puts all this data in the NGA file.
The NGDBuild program performs all the steps necessary to read a netlist file in XNF or EDIF format and create an NGD file describing the logical design. The NGDBuild program executes as the Translate step within the Flow Engine.
An NGD (native generic database) file is an output from the NGDBuild run. An NGD file contains a logical description of the design expressed both in terms of the hierarchy used when the design was first created and in terms of lower-level Xilinx primitives to which the hierarchy resolves.
An NGM (native generic mapping) file is an output from the MAP run and contains mapping information for the design. The NGM file is an input file to the NGDAnno program.
For state machines, in one-hot encoding, an individual state register is dedicated to one state. Only one flip-flop is active, or hot, at any one time.
Optimization is the process that decreases the area or increases the speed of a design. Foundation allows you to control optimization of a design on a module-by-module basis. This means that you have the ability to, for instance, optimize certain modules of your design for speed, some for area, and some for a balance of both.
PAR is a program that takes an NCD file, places and routes the design, and outputs an NCD file. The NCD file produced by PAR can be used as a guide file for reiterative placement and routing. The NCD file can also be used by the bitstream generator, BitGen.
A path delay is the time it takes for a signal to propagate through a path.
The PCF file is an output file of the MAP program. It is an ASCII file containing physical constraints created by the MAP program as well as physical constraints entered by you. You can edit the PCF file from within EPIC. (FPGA only)
Project Description File. The PDF file contains library and other project-specific information. Not to be confused with an Adobe Acrobat document with the same extension.
Physical Design Rule Check (DRC) is a series of tests to discover logical and physical errors in the design. Physical DRC is applied from EPIC, BitGen, PAR, and Hardware Debugger. By default, results of the DRC are written into the current working directory.
A physical macro is a logical function that has been created from components of a specific device family. Physical macros are stored in files with the extension .nmc. A physical macro is created when EPIC is in macro mode. See also “macro.”
A pin can be a symbol pin or a package pin. A package pin is a physical connector on an integrated circuit package that carries signals into and out of an integrated circuit. A symbol pin, also referred to as an instance pin, is the connection point of an instance to a net.
Pinwires are wires which are directly tied to the pin of a site (CLB, IOB, etc.)
Foundation organizes related files into a distinct logical unit called a project, which contains a variety of file types. A project is created as either a Schematic Flow or an HDL Flow project.
The right-hand portion of the Foundation Project Manager that provides access to the synthesis and implementation tools, and the current design project. The project flowchart can display up to four tabs: Flow, Contents, Reports, and Synthesis (Schematic Flow only).
The Project Manager, the overall Foundation project management tool, contains the Foundation Series tools used in the design process.
The PROM File Formatter is the program used to format one or more bitstreams into an MC86, TEKHEX, EXORmacs or HEX PROM file format.
The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.
A route that can pass through an occupied or an unoccupied CLB site is called a route-through. You can manually do a route-through in EPIC. Route-throughs provide you with routing resources that would otherwise be unavailable.
The schematic design tool accessed by selecting the Schematic Capture icon on the Design Entry button in the Project Manager.
A project that uses the Schematic Flow can have top-level schematic, ABEL, or state machine files. It can contain underlying schematic, HDL (VHDL, Verilog, or ABEL), state machine designs, or netlists.
A state diagram is a pictorial description of state relationships.
State machine designs typically start with the translation of a concept into a “paper design,” usually in the form of a state diagram or a bubble diagram. The paper design is converted to a state table and, finally, into the source code itself.
The values stored in the memory elements of a device (flip-flops, RAMs, CLB outputs, and IOBs) that represent the state of that device for a particular readback (time). To each state, there corresponds a specific set of logical values.
With the Symbol Editor, you can edit features of component symbols such as pin locations, pin names, pin numbers, pin shape, and pin descriptions for component symbols.
Synopsys supports HDL, a behavioral language for entering equations. HDL also enables you to include LogiBLOX schematic components in a design.
The HDL design process in which each design module is elaborated and the design hierarchy is created and linked to form a unique design implementation. Synthesis starts from a high level of logic abstraction (typically Verilog or VHDL) and automatically creates a lower level of logic abstraction using a library containing primitives
See Express Time Tracker.
Transitions define the movement from one state to another in a state machine. They are drawn as arrows between state bubbles.
TRCE (Timing Reporter and Circuit Evaluator) “trace” is a program that will automatically perform a static timing analysis on a design using the specified (either timing constraints. The input to TRCE is an NCD file and, optionally, a PCF file. The output from TRCE is an ASCII timing report which indicates how well the timing constraints for your design have been met.
A TWR (Timing Wizard Report) file is an output from the TRCE program. A TWR file contains a logical description of the design expressed both in terms of the hierarchy used when the design was first created and in terms of lower-level Xilinx primitives to which the hierarchy resolves.
A UCF (user constraints file) contains user-specified logical constraints.
Verification is the process of reading back the configuration data of a device and comparing it to the original design to ensure that all of the design was correctly received by the device.
Verilog is a commonly used Hardware Description Language (HDL) that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. It is IEEE standard 1364-1995. Foundation Express and Base Express products include design entry tools to create Verilog designs.
VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High-Speed Integrated Circuits). An industry-standard (IEEE 1076.1) HDL. Recognizable as a file with a .vhd or .vhdl extension.
VHDL can be used to model a digital system at many levels of abstraction ranging form the algorithmic level to the gate level. It is IEEE standard 1076-1987. Foundation Express and Base Express products include design entry tools to create VHDL designs.
A wire is either a net or a signal.
XABEL is a Xilinx-specific version of the ABEL design entry software. It uses Boolean equations, truth tables, and state machines to create modules and full designs for CPLDs and modules for FPGAs.
A GUI tool that you can use to enter design constraints. The Xilinx Constraints Editor is integrated with the Design Implementation tools and available in all product configurations.
In Foundation 1.4, this compiler synthesizes and generates EDIF 2 0 0 from Metamor VHDL code or state machine designs. It has been replaced by the Synopsys FPGA Express compiler for Foundation Series F1.5.
