Appendix D

File Processing Overview

This section shows the files created/used by Foundation to process FPGA and CPLD designs. These figures represent 1) a high-level overview of Foundation's processing tools and 2) the manipulation of the various netlist and constraint files by these tools.

FPGAs

The following three figures illustrate the processing that Foundation performs to create FPGA designs.

Figure D.1 Manipulation of Netlist and Constraint Files for FPGAs (Part 1)

Figure D.2 Manipulation of Netlist and Constraint Files for FPGAs (Part 2)

Figure D.3 Manipulation of Netlist and Constraint Files for FPGAs (Part 3)

CPLDs

The following three figures illustrate the processing that Foundation performs to create CPLD designs.

Figure D.4 Manipulation of Netlist and Constraint Files for CPLDs (Part 1)

Figure D.5 Manipulation of Netlist and Constraint Files for CPLDs (Part 2)

Figure D.6 Manipulation of Netlist and Constraint Files for CPLDs (Part 3)