Appendix C

Instantiated Components

This appendix lists the Xilinx Unified Library components most frequently instantiated in synthesis designs for FPGAs. This appendix contains the following sections:

• “Library/Architecture Definitions”
  
  
• “STARTUP Component”
  
  
• “BSCAN Component”
  
  
• “READBACK Component”
  
  
• “RAM and ROM”
  
  
• “Global Buffers”
  
  
• “Fast Output Primitives (XC4000X only)”
  
  
• “IOB Components”
  
  

The function of each component is briefly described and the pin names are supplied, along with a listing of the Xilinx product families involved. Associated instantiation can be used to include the component in an HDL design. For complete lists of the Xilinx components, see the online Libraries Guide.

Library/Architecture Definitions

The following subsections describe which Xilinx architectural families are included in each library.

XC3000 Library

Information appearing under the title of XC3000 pertains to the XC3000A and XC3100A families. This includes the XC3000L and XC3100L, which are identical in architecture and features to the XC3000A and XC3100A, respectively, but operate at a nominal supply voltage of 3.3 V.

XC4000E Library

Wherever XC4000E is mentioned, it includes the XC4000E and XC4000L families. The XC4000L is identical in architecture and features to the XC4000E but operates at a nominal supply voltage of 3.3 V.

XC4000X Library

Information under the title XC4000X pertains to the XC4000EX, XC4000XL, XC4000XV, and XC4000XLA families. The XC4000XL is identical in architecture and features to the XC4000EX but operates at a nominal supply voltage of 3.3 V. The XC4000XV has identical library symbols to the XC4000EX and XC4000XL but operates at a nominal supply voltage of 2.5 V and includes additional features (the DRIVE attribute).

XC5200 Library

The title XC5200 pertains to the XC5200 family.

XC9000 Library

The title XC9000 pertains to the XC9500 and XC9500XL CPLD families.

Spartan Library

The Spartan library pertains to the Spartan family XCS* devices.

SpartanXL Library

The SpatanXL library pertains to the SpartanXL family XCS*XL devces.

Virtex Library

The Virtex Library pertains to the Virtex family XCV* devices.

STARTUP Component

The STARTUP component is typically used to access the global set/reset and global 3-state signals. STARTUP can also be used to access the startup sequence clock.

For information on the startup sequence and the associated signals, see the Programmable Logic Data Book and the online Libraries Guide.

Table C_1 Design STARTUP Components

BSCAN Component

To use the boundary-scan (BSCAN) circuitry in a Xilinx FPGA, the BSCAN component must be present in the input design. The TDI, TDO, TMS, and TCK components are typically used to access the reserved boundary scan device pads for use with the BSCAN component but can be connected to user logic as well. For more information on the BSCAN component, the internal boundary scan circuitry, and the directional properties of the four reserved boundary scan pads, refer to Programmable Logic Data Book and the online Libraries Guide.

Table C_2 Boundary Scan Components

READBACK Component

To use the dedicated readback logic in a Xilinx FPGA, the READBACK component must be inserted in the input design. The MD0, MD1, and MD2 components are typically used to access the mode pins for use with the readback logic but can be connected to user logic as well. For more information on the READBACK component, the internal readback logic, and the directional properties of the three reserved mode pins, see the Programmable Logic Data Book and the online Libraries Guide.

Table C_3 Readback Components

RAM and ROM

Some of the most frequently instantiated library components are the RAM and ROM primitives. Because most synthesis tools are unable to infer RAM or ROM components from the source HDL, the primitives must be used to build up more complex structures. The following list of RAM and ROM components is a complete list of the primitives available in the Xilinx library. For more information on the components, see the Programmable Logic Data Book and the online Libraries Guide.

Table C_4 Memory Components

Global Buffers

Each Xilinx PLD device has multiple styles of global buffers; the XC4000EX devices have 20 actual global buffers - eight BUFGLSs, eight BUFEs, and four BUFFCLKs. For some designs it may be necessary to use the exact buffer desired to ensure appropriate clock distribution delay.

For most designs, the BUFG, BUFGS, and BUFGP components can be inferred or instantiated, thus allowing the design implementation tools to make an appropriate physical buffer allocation. For more information on the components, see the Programmable Logic Data Book.

Table C_5 Global Buffer Components

Fast Output Primitives (XC4000X only)

One of the features added to the XC4000X architecture is the fast output MUX. There is one fast output MUX located in each IOB which can be used to implement any two input logic functions. Each component can have zero, one, or two inverted inputs. Because the output MUX is located in the IOB, it must be connected to the input pin of either an OBUF or an OBUT. For more information on the output primitives, see the Programmable Logic Data Book.

NOTE

For information on how to instantiate output MUXs with inverted inputs, see the Synopsys (XSI) Interface/ Tutorial Guide.

Table C_6 Fast Output Primitives

IOB Components

Depending on the synthesis vendor being used, some IOB components must be instantiated directly in the input design. Most synthesis tools support IOB D-type flip-flop inferences but may not yet support IOB D-type flip-flop inference with clock enables. Because there are many slew rates and delay types available, there are many derivatives of the primitives shown. For a complete list of the IOB primitives, see the online Libraries Guide.

Table C_7 Input/Output Block Components