Schematic Flow projects require top-level schematic, ABEL, LogiBLOX, or State Machine designs. The top-level design can have any number of underlying schematic, HDL, LogiBLOX, ABEL, or Finite State Machine (FSM) macros. Although individual modules may require some form of synthesis, the entire project is not synthesized and the netlist that is exported for implementation is not optimized as in an HDL Flow project.
