Hardware Description Languages

Hardware description languages (HDLs) describe the architecture and behavior of discrete electronic systems. Modern HDLs and their associated simulators are very powerful tools for integrated circuit designers.

A typical HDL supports a mixed-level description in which gate and netlist constructs are used with functional descriptions. This mixed-level capability enables you to describe system architectures at a very high level of abstraction, then incrementally refine a design's detailed gate-level implementation.

HDL descriptions play an important role in modern design methodology for three main reasons.

• You can verify design functionality early in the design process. A design written as an HDL description can be simulated immediately. Design simulation at this higher level, before implementation at the gate-level, allows you to evaluate architectural and design decisions.
  
  
• Using Foundation Express to compile Verilog and synthesize logic, you can automatically convert an HDL description to a gate-level implementation in a target FPGA or CPLD technology. This step eliminates the former technology-specific design bottleneck, the majority of circuit design time, and the errors introduced when you hand translate an HDL specification to gates.
  
  
• With Foundation Express logic optimization, you can automatically transform a synthesized design into a smaller or faster circuit. Foundation Express both synthesizes and optimizes logic. For further information, refer to the Foundation Express online help.
  
  
• An HDL description is more easily read and understood than a netlist or schematic description. HDL descriptions provide technology independent documentation of a design and its functionality. Because the initial HDL design description is technology independent, you can use it again to generate the design in a different technology, without having to translate it from the original technology.