Using Foundation to Compile a Verilog HDL Design

Verilog Reference GuideChapter 1: Foundation Express with Verilog HDL

Using Foundation to Compile a Verilog HDL Design

When a Verilog design is read into Foundation Express, it is converted to an internal database format so that Foundation Express can synthesize and optimize the design. When Foundation Express optimizes a design, it may restructure part or all of the design. You control the degree of restructuring. You have the following options.

Fully preserve a design's hierarchy
Combine certain modules with others
Compress the entire design into one module (called flattening the design), if it is beneficial

The following section describes the design process that uses Foundation Express with a Verilog HDL simulator.