Design Methodology

The figure below shows a typical design process that uses Foundation Express and a Verilog HDL simulator. Each step of this design model is described in detail after the figure.

Figure 1.2 Design Flow

The following numbered steps correspond to the numbers in the figure above.

1. Write a design description in the Verilog language.
   
   This description can be a combination of structural and functional elements (as shown in the “Description Styles” chapter). It is used with both Foundation Express and a Verilog simulator.
   
   
2. Write Verilog language test drivers for the Verilog HDL simulator.
   
   The drivers supply test vectors for simulation and gather output data. For information on writing these drivers, see the appropriate simulator manual.
   
   
3. Simulate the design by using a Verilog HDL simulator, and verify that the description is correct.
   
   
4. Synthesize and optimize the Verilog design description into a gate-level netlist using Foundation Express.
   
   Foundation Express generates optimized netlists to satisfy timing constraints for a targeted FPGA architecture.
   
   
5. Map and, then, place and route the FPGA netlist using your FPGA development system. Generate a Verilog netlist for post-place and route simulation.
   
   The development system includes simulation models and interfaces required for the design flow.
   
   
6. Simulate the technology-specific version of the design with the Verilog simulator.
   
   You can use the original Verilog simulation drivers from Step 3 because module and port definitions are preserved through the translation and optimization processes.
   
   
7. Compare the output of the gate-level simulation (Step 6) with the output of the original Verilog description simulation (Step 3) to verify that the implementation is correct.