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Verilog Reference Guide
Chapter 4: Expressions

Constant-Valued Expressions

A constant-valued expression is an expression whose operands are either constants or parameters. Foundation Express determines the value of these expressions.

In the following example, size-1 is a constant-valued expression. The expression (op == ADD) ? a+b : a-b is not a constant-valued expression because the value depends on the variable op. If the value of op is 1, b is added to a; otherwise, b is subtracted from a.

//all expressions are constant-valued, 
//except in the assign statement.
module add_or_subtract(a,b,op,s);
//performs s=a+b if op is ADD
// s=a-b if op is not ADD
   parameter size=8;
   parameter ADD=1'b1;

   input op; 
   input [size-1:0]a,b;
   output[size-1:0]s;
   assign s=(op==ADD)? a+b:a-b;   //not a constant-
                                 //valued expression
endmodule

The operators and operands used in an expression influence the way that a design is synthesized. Foundation Express evaluates constant-valued expressions and does not synthesize circuitry to compute their value. If an expression contains constants, they are propagated to reduce the amount of circuitry required. However, Foundation Express does synthesize circuitry for an expression that contains variables.