Verilog Reference Guide
Chapter 4: Expressions

## Expression Bit Widths

The bit width of an expression depends on the widths of the operands and the types of operators in the expression.

The “Expression Bit-Widths” table shows the bit-width for each operand and operator. In the table, i, j, and k are expressions; L(i) is the bit-width of expression i.

To preserve significant bits within an expression, Verilog fills in zeros for smaller-width operands. The rules for this zero-extension depend on the operand type. These rules are also listed in the “Expression Bit-Widths” table.

Verilog classifies expressions (and operands) as either self-determined or context-determined. A self-determined expression is one in which the width of the operands is determined solely by the expression itself. These operand widths are never extended.

#### Table 4_3 Expression Bit-Widths

Expression
Bit Length
unsized constant
32-bit
self-determined
sized constant
as specified
self-determined
i + j
max(L(i),L(j))
context-determined
i - j
max(L(i),L(j))
context-determined
i * j
max(L(i),L(j))
context-determined
i / j
max(L(i),L(j))
context-determined
i % j
max(L(i),L(j))
context-determined
i & j
max(L(i),L(j))
context-determined
i | j
max(L(i),L(j))
context-determined
i ^ j
max(L(i),L(j))
context-determined
i ^~ j
max(L(i),L(j))
context-determined
~i
L(i)
context-determined
i == j
1-bit
self-determined
i !== j
1-bit
self-determined
i && j
1-bit
self-determined
i || j
1-bit
self-determined
i > j
1-bit
self-determined
i >= j
1-bit
self-determined
i < j
1-bit
self-determined
i <= j
1-bit
self-determined
&i
1-bit
self-determined
|i
1-bit
self-determined
^i
1-bit
self-determined
~&i
1-bit
self-determined
~|i
1-bit
self-determined
~^i
1-bit
self-determined
i >> j
L(i)
j is self-determined
{i{j}}
i*L(j)
j is self-determined
i << j
L(i)
j is self-determined
i ? j : k
Max(L(j),L(k))
j is self-determined
{i,...,j}
L(i)+...+L(j)
self-determined
{i {j,...,k}}
/*(L(j)+...+L(k))
self-determined

The following example shows a self-determined expression that is a concatenation of variables with known widths.

```output [7:0] result;
wire   [3:0] temp;
```

```assign temp = 4'b1111;
assign result = {temp,temp};```

The concatenation has two operands. Each operand has a width of four bits and a value of 4'b1111. The resulting width of the concatenation is 8 bits, which is the sum of the width of the operands. The value of the concatenation is 8'b11111111.

A context-determined expression is one in which the width of the expression depends on all operand widths in the expression. For example, Verilog defines the resulting width of an addition as the greater of the widths of its two operands. The addition of two 8-bit quantities produces an 8-bit value; however, if the result of the addition is assigned to a 9-bit quantity, the addition produces a 9-bit result. Because the addition operands are context-determined, they are zero-extended to the width of the largest quantity in the entire expression.

The following example shows context-determined expressions.

```if (((1'b1 << 15) >> 15) = = 1'b0)
//This expression is ALWAYS true.
```

```if ((((1'b1 << 15) >> 15)| 20'b0) = = 1'b0)
//This expression is NEVER true.```

The expression ((1'b1 << 15) >> 15) produces a 1-bit 0 value (1'b0). The 1 is shifted off of the left end of the vector, producing a value of 0. The right shift has no additional effect. For a shift operator, the first operand (1'b1) is context-dependent; the second operand (15) is self-determined.

The expression (((1'b1 << 15) >> 15) | 20'b0) produces a 20-bit 1 value (20'b1). 20'b1 has a 1 in the least significant bit position and 0s in the other 19 bit positions. Because the largest operand within the expression has a width of 20, the first operand of the shift is zero-extended to a 20-bit value. The left shift of 15 does not drop the 1 value off the left end; the right shift brings the 1 value back to the right end, resulting in a 20-bit 1 value (20'b1).