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The // synopsys translate_off and // synopsys translate_on directives tell Foundation Express to suspend translation of the source code and restart translation at a later point. Use these directives when your Verilog source code contains commands specific to simulation that Foundation Express does not accept.
You turn translation off with the either of the following directives.
// synopsys translate_off
/* synopsys translate_off */
You turn translation back on with either of the following directives.
// synopsys translate_on
/* synopsys translate_on */
At the beginning of each Verilog file, translation is enabled. After that, you can use the translate_off and translate_on directives anywhere in the text. These directives must be used in pairs. Each translate_off must appear before its corresponding translate_on. The following example shows a simulation driver protected by a translate_off directive.
module trivial (a, b, f);
input a,b;
output f;
assign f = a & b;
// synopsys translate_off
initial $monitor (a, b, f);
// synopsys translate_on
endmodule
/* synopsys translate_off */
module driver;
reg [1:0] value_in;
integer i;
trivial triv1(value_in[1], value_in[0]);
initial begin
for (i = 0; i < 4; i = i + 1)
#10 value_in = i;
end
endmodule
/* synopsys translate_on */