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Verilog Reference Guide
Chapter 7: Foundation Express Directives

parallel_case Directive

The // synopsys parallel_case directive affects the way logic is generated for the case statement. As explained in the “Full Case and Parallel Case” section of the “Functional Descriptions” chapter, a case statement generates the logic for a priority encoder. Under certain circumstances, you might not want to build a priority encoder to handle a case statement. You can use the parallel_case directive to force Foundation Express to generate multiplexer logic instead.

The syntax for the parallel_case directive is either of the following directives.

// synopsys parallel_case

or

/* synopsys parallel_case */

In the following example, the states of a state machine are encoded as one hot signal. If the case statement in the example were implemented as a priority encoder, the generated logic would be unnecessarily complex.

reg [3:0] current_state, next_state;
parameter state1 = 4'b0001, state2 = 4'b0010,
   state3 = 4'b0100, state4 = 4'b1000;

case (1)//synopsys parallel_case

   current_state[0] : next_state = state2;
   current_state[1] : next_state = state3;
   current_state[2] : next_state = state4;
   current_state[3] : next_state = state1;

endcase

Use the parallel_case directive immediately after the case expression, as shown above. This directive makes all case-item evaluations in parallel. All case items that evaluate to TRUE are executed (not just the first one) which might give you unexpected results.)

In general, use parallel_case when you know that only one case item is executed. If only one case item is executed, the logic generated from a parallel_case directive performs the same function as the circuit when it is simulated. If two case items are executed, and you have used the parallel_case directive, the generated logic is not the same as the simulated description.