|
|
|
|
|
In Verilog, you cannot instantiate modules in behavioral code. To include an embedded netlist in your behavioral code, use the directives // synopsys map_to_module and // synopsys return_port_name for Foundation Express to recognize the netlist as a function being implemented by another module. When this subprogram is invoked in the behavioral code, the module is instantiated.
The first directive, // synopsys map_to_module, flags a function for implementation as a distinct component. The syntax follows.
// synopsys map_to_module modulename
The second directive identifies a return port, because functions in Verilog do not have output ports. A return port name must be identified to instantiate the function as a component. The syntax follows.
// synopsys return_port_name portname
Note: Remember that if you add a map_to_module directive to a function, the contents of the function are parsed and ignored and the indicated module is instantiated. You must ensure that the functionality of the module instantiated in this way and the function it replaces are the same; otherwise, pre-synthesis and post-synthesis simulation do not match.
The following example illustrates the map_to_module and return_port_name directives.
module mux_inst (a, b, c, d, e);
input a, b, c, d;
output e;
function mux_func;
// synopsys map_to_module mux_module
// synopsys return_port_name mux_ret
input in1, in2, cntrl;
/*
** the contents of this function are ignored for
** synthesis, but the behavior of this function
** must match the behavior of mux_module for
** simulation purposes
*/
begin
if (cntrl) mux_func = in1;
else mux_func = in2;
end
endfunction
assign e = a & mux_func (b, c, d);
//this function call actually instantiates component //(module) mux_module
endmodule
module mux_module (in1, in2, cntrl, mux_ret);
input in1, in2, cntrl;
output mux_ret;
and and2_0 (wire1, in1, cntrl);
not not1 (not_cntrl, cntrl);
and and2_1 (wire2, in2, not_cntrl);
or or2 (mux_ret, wire1, wire2);
endmodule