Chapter 8

Writing Circuit Descriptions

You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the synthesized circuit's area and speed. The way you write your Verilog source code can affect synthesis.

This chapter describes how to write a Verilog description to ensure an efficient implementation. Topics include the following.

• “How Statements Are Mapped to Logic”
  
  
• “Don't Care Inference”
  
  
• “Propagating Constants”
  
  
• “Synthesis Issues”
  
  
• “Designing for Overall Efficiency”
  
  

Here are some general guidelines for writing efficient circuit descriptions:

• Restructure a design that makes repeated use of several large components to minimize the number of instantiations.
  
  
• In a design that needs some, but not all, of its variables or signals stored during operation, minimize the number of latches or flip-flops required.
  
  
• Consider collapsing hierarchy for more efficient synthesis.