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The next two sections describe feedback paths and latches that result from ambiguities in signal or variable assignments and asynchronous behavior.
Sometimes your Verilog source can imply combinatorial feedback paths or latches in synthesized logic. This happens when a signal or a variable in a combinatorial logic block (an always block without a posedge or negedge clock statement) is not fully specified. A variable or signal is fully specified when it is assigned under all possible conditions.
In a synchronous design, all registers use the same clock signal. That clock signal must be a primary input to the design. A synchronous design has no combinatorial feedback paths, one-shots, or delay lines. Synchronous designs perform the same function regardless of the clock rate, as long as the rate is slow enough to allow signals to propagate all the way through the combinatorial logic between registers.
Foundation Express synthesis tools offer limited support for asynchronous designs. The most common way to produce asynchronous logic in Verilog is to use gated clocks on registers. If you use asynchronous design techniques, synthesis and simulation results might not agree. Because Foundation Express does not issue warning messages for asynchronous designs, you are responsible for verifying the correctness of your circuit.
The following examples show two approaches to the same counter design: The first example is synchronous, and the second example is asynchronous.
module COUNT (RESET, ENABLE, CLK, Z);
input RESET, ENABLE, CLK;
output [2:0] Z;
reg [2:0] Z;
always @ (posedge CLK) begin
if (RESET) begin
Z = 3'b0;
end else if (ENABLE == 1'b1) begin
if (Z == 3'd7) begin
Z = 3'b0;
end else begin
Z = Z + 3'b1;
end
end
end
endmodule
The following example shows an asynchronous counter design.
module COUNT (RESET, ENABLE, CLK, Z);
input RESET, ENABLE, CLK;
output [2:0] Z;
reg [2:0] Z;
wire GATED_CLK = CLK & ENABLE;
always @ (posedge GATED_CLK or posedge RESET) begin
if (RESET) begin
Z = 3'b0;
end else begin
if (Z == 3'd7) begin
Z = 3'b0;
end else begin
Z = Z + 3'b1;
end
end
end
endmodule
The asynchronous version of the design uses two asynchronous design techniques. The first technique is to enable the counter by ANDing the clock with the enable line. The second technique is to use an asynchronous reset. These techniques work if the proper timing relationships exist between the asynchronous control lines (ENABLE and RESET) and the clock (CLK) and if the control lines are glitch-free.
Some forms of asynchronous behavior are not supported. For example, you might expect the following circuit description of a one-shot signal generator to generate three inverters (an inverting delay line) and a NAND gate.
X = A ~& (~(~(~ A)));
However, this circuit description is optimized to the following.
X = A ~& (~ A); then X = 1;