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The efficiency of a synthesized design depends primarily on how you describe its component structure. The next two sections explain how to describe random logic and how to share complex operators.
You can describe random logic with many different shorthand Verilog expressions. Foundation Express often generates the same optimized logic for equivalent expressions, so your description style for random logic does not affect the efficiency of the circuit. The following example shows four groups of statements that are equivalent. (Assume that a, b, and c are 4-bit variables.) Foundation Express creates the same optimized logic in all four cases.
c = a & b;
c[3:0] = a[3:0] & b[3:0];
c[3] = a[3] & b[3];
c[2] = a[2] & b[2];
c[1] = a[1] & b[1];
c[0] = a[0] & b[0];
for (i = 0; i <= 3; i = i + 1)
c[i] = a[i] & b[i];
You can use automatic resource sharing to share most operators. However, some complex operators can be shared only if you rewrite your source description more efficiently. These operators follow.
The following example shows a circuit description that creates more functional units than necessary when automatic resource sharing is turned off.
module rs(a, i, j, c, y, z);
input [7:0] a;
input [2:0] i,j;
input c;
output y, z;
reg y, z;
always @(a or i or j or c)
begin
z=0;
y=0;
if(c)
begin
z = a[i];
end
else
begin
y = a[j];
end
end
endmodule
The schematic for this code description is shown in the following figure.
Figure 8.14 Circuit Schematic with Two Array IndexesYou can rewrite the circuit description in the above example so that it contains only one array index, as shown in the following example. The circuit in the following example is more efficient than that in the above example, since it uses a temporary register, temp, to store the value evaluated in the if statement.
module rs1(a, i, j, c, y, z);
input [7:0] a;
input [2:0] i,j;
input c;
output y, z;
reg y, z;
reg [3:0] index;
reg temp;
always @(a or i or j or c) begin
if(c)
begin
index = i;
end
else
begin
index = j;
end
temp = a[index];
z=0;
y=0;
if(c)
begin
z = temp;
end
else
begin
y = temp;
end
end
endmodule
The schematic is shown in the following figure.
Figure 8.15 Circuit Schematic with One-Array IndexConsider resource sharing whenever you use a complex operation more than once. Complex operations include adders, multipliers, shifters (only when shifting by a variable amount), comparators, and most user-defined functions.