Click the Configuration, Startup, Readback, Tie, or Advanced tab to access the different options within the Configuration Template dialog box. Use the different tabs of this dialog box to set the options described in this section.
Click OK to accept the template, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.
Use the Configuration tab, shown in the following figure, to set these options.
Figure 5.40 XC4000 Configuration Template Configuration Tab |
The XC4000 uses an internal configuration clock, CCLK, when configuring in a master mode. The configuration rate option allows you to select the rate for this clock. The following options are available. The default is Slow.
The Threshold Levels field contains the following options.
These options are supported for the XC4000E and XC4000EX subfamilies only.
The Configuration Pins field contains the following options.
This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.
This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.
Use the Startup tab, shown in the following figure, to set the configuration startup options.
Figure 5.41 XC4000 Configuration Template Startup Tab |
The XC4000 Startup tab is identical to the tab described in the Spartan Startup Tab section.
Use the Readback tab, shown in the following figure, to set the configuration readback options.
Figure 5.42 XC4000 Configuration Template Readback Tab |
The XC4000 Readback tab is identical to the tab described in the Spartan Readback Tab section.
Use the Tie tab, shown in the following figure, to set the tie options.
Figure 5.43 XC4000 Configuration Template Tie Tab |
The X4000 Tie tab is identical to the tab described in the Spartan Tie Tab section.
Use the Advanced tab, shown in the following figure, to set these options.
Figure 5.44 XC4000 Configuration Template Advanced Tab |
Use the Configuration Address Lines option to set the number of address lines that will be used by the FPGA during device configuration. Address lines are used to address data from a parallel PROM or flash memory device. Select either 18 or 22. If you choose 22, four extra device pins are activated as configuration address lines. The default is 18.
This option only applies to master parallel mode configuration. For XC4000EX devices, you must set this option in addition to setting the mode pins. Refer to the Programmable Logic Data Book for more information on address lines and master parallel mode configuration.
For XC4000XL and XC4000XV devices, the address lines are automatically set to 22 when you set the mode pins for master parallel mode configuration.