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Verifying the Design

Use the following two EPIC tools to verify your design.

Physical Design Rule Check (DRC)

Physical Design Rule Check (DRC) is a series of tests to discover logical and physical errors in your design. Physical DRC is applied to EPIC and BITGEN.

In addition to running in EPIC, the DRC runs during these conditions.

The DRC runs transparently.

Results of the DRC are written into the history area. DRC messages can be error messages for conditions where the routing or component logic does not operate correctly, or warnings for conditions where the routing or logic are incomplete.

DRC runs can produce a large number of messages. Because the history area can only contain a total of 2,000 lines of text, you may not be able to scroll to messages at the beginning of a DRC run or to messages from previous runs. If you want to view them, use a text editor such as, vi on a workstation or Microsoft Windows Notepad on a PC to view the contents of the log file for your session. This file, design_name.epl, is described in the “Recovering an Aborted EPIC Session” section. You must remain in EPIC while you view this file, because the file is eliminated when you exit EPIC.

There are two ways to run the DRC, by either posting a dialog box or by performing the DRC command.

To run the DRC from a dialog box follow these steps.

  1. Select the objects on which you will run the DRC.

    Select any combination of components, net pins, route segments, or nets. You can also run DRC with nothing selected, if you want to check all objects in the design.

  2. Select the Post DRC option from the Tools menu or type post drc in the EPIC Command Line dialog box.

    The DRC dialog box appears.

    Figure 3.29 DRC Dialog Box

  3. Select the corresponding button to perform a Net Check, a Block Check, a Chip Check, or All Checks

    You can select only one.

  4. Select the corresponding button to perform the DRC on All objects in the design or only on Selected Objects.

  5. Select All for all DRC messages, errors and warnings or Errors Only.

  6. Click Apply or OK.

The DRC tests are performed on the specified objects.

To run the DRC without the dialog box use this procedure.

  1. Select the objects on which you will run the DRC.

    Select any combination of components, net pins, route segments, or nets. You can also run DRC with nothing selected, if you want to check all objects in the design.

  2. Perform the DRC command in any of the following ways.

The DRC tests are performed on the objects you specified. The tests follow these rules.

If you perform the DRC from the EPIC Command Line dialog box, you can enter options to the DRC command. These options are described in the “DRC” section of the “Command Line Syntax” chapter.

Delay Calculator

Delay is the time that it takes to propagate a signal from a driver pin to a load pin. If not otherwise indicated, delay values are given in nanoseconds.

The Delay Calculator tool calculates and displays the delay associated with load and driver pins in a given net or path.

Net Delay Calculation

You can either find the delay for all pins in the net or for specific pins.

To display the delay for all pins in a net follow these steps.

  1. Select a net name from the EPIC List dialog box or type select net net_name on the EPIC command line.

  2. Select the Delay push button, or type the delay command in the EPIC command line.

    See the “Delay” section of the “Command Line Syntax” chapter. If the net is fully or partially routed, a list of pins appears in the history area, along with their associated delays. If the net is unrouted, each pin is listed as “unrouted.”

  3. Select the Attrib push button.

    The Net Attributes dialog box appears.

  4. From the Net Attributes dialog box, select Show Pin List.

The Pin List dialog box appears. It displays the delays for associated pins as shown in the “Pin List Dialog Box” figure.

If a blank space appears next to a pin name, either in the Pin List or in the history area, the pin is the net driver that has no delay or the pin is unrouted. A tilde (~) appearing with a delay, indicates that the value shown is approximate.


NOTE

When you display delays for all of the pins in a net, the net is deselected if the Automatic Deselect Option in the Main Window Attribute dialog box is turned On.


To display the delays for selected pins in a net, use the mouse to select the specific pins. If the net is fully or partially routed, the delays for the selected pins are automatically displayed in the history area. If the net is unrouted, no delays appear.

Path Delay Calculation

To display the delay between two pins in a path follow these steps.

  1. Using the mouse, select the two pins.

  2. Select the Delay push button.

    The path delay between the two pins is displayed in the history area. If there are multiple paths between the two pins, the path with the maximum delay appears. If Auto Highlight is enabled, the path between the pins is highlighted.

    Alternatively, with the pins selected, type one of the following commands in the EPIC Command Line dialog box.

TRACE

You can run TRACE (Timing Reporter and Circuit Evaluator) from within EPIC, to visualize timing errors and to make modifications without going back and forth between EPIC and TRACE. You can run TRACE within EPIC in two ways: from the Tools menu or from the command line.

Functions performed by TRACE in EPIC are the same as those outside of EPIC with a few exceptions, which are noted in this section.

TRACE functionality within EPIC includes the following.

Input and Output Files

Input to TRACE is the currently loaded design and the constraint file.

Output is sent to the history area, unless you specify otherwise, and to the EPL (log) file instead of to a timing report (TWR) file.

Selecting Constraints for Timing Analysis

Before running TRACE in EPIC, select the constraints you want TRACE to analyze.


NOTE

TRACE only operates on timing constraints and on the Define Path, Define Startpoint, and Define Endpoint constraints. If you select any other type of constraint and run TRACE, an error results.


There are two ways to select constraints.

Running TRACE from the Tools Menu

To run TRACE from the EPIC Tools menu follow these steps.

  1. Select the constraint(s) that you want TRACE to analyze as described in the “Selecting Constraints for Timing Analysis” section.

  2. Select Post Trace from the Tools menu.

    The TRACE dialog box appears.

    Figure 3.31 TRACE Dialog Box

    Fields in the TRACE dialog box are as follows.

    Report
    Select either an Error Timing Report or a Verbose Timing Report.
    Limit
    Enter a number 1 or greater. Limits the number of errors reported (or the extent of verbose reporting) for each selected constraint.
    Do Not Display Report in History Window
    Suppresses display of the report in the EPIC history area.



  3. Make your entries in the TRACE dialog box, then click OK or Apply.

    TRACE runs timing analysis on the constraints that you selected. The following dialog box appears.

    Figure 3.32 TRACE Summary Dialog Box

    The TRACE Summary dialog box lists information on each of the selected constraints for the TRACE run. Information is divided into three columns.

    #Items
    Number of nets and components involved in the analysis.
    Errors
    Number of timing errors found on a particular constraint.
    Constraint
    Signifies the constraint being analyzed.



    For additional timing information on any of the constraints listed in the Summary dialog box, click on the listed constraint. The TRACE Error dialog box appears.

    Figure 3.33 TRACE Error Dialog Box

    The fields in this dialog box are as follows.

    Constraint
    Displays the constraint. You cannot modify this field or the Summary field, but you can scroll either field horizontally.
    Summary
    Displays a one-line summary of the constraint.
    Items
    This scrollable list enumerates the paths in the error or verbose report. The number to the right of the path specification is the amount of slack, indicating whether an actual delay is greater or less than its constraint. A minus sign preceding the time indicates an error.
    Report
    Outputs the detailed TRACE report for the selected path to the history area and to the EPL (log) file.
    Unhilite
    Unhighlights the selected path in the EPIC window.
    Hilite
    Highlights the selected path, using the color specified in the Color field.
    Color
    Specifies a color in which to highlight an error in the EPIC window. You can use different colors for different errors.




    NOTE

    You can also use the Hilite command to display errors in the EPIC editing area and the Unhilite command to erase the display. See the “Hilite” section of the “Command Line Syntax” chapter.


Running TRACE from the Command Line

This section describes how to run TRACE from the EPIC Command Line. The TRACE command displays a timing report in the history area (unless you specify otherwise) on selected constraints. The report is also saved in an EPL file. You can specify an error report or a verbose report and set a limit to the number of errors reported.

trace [-r] [-e] [-l limit: 0-32000]

If no options are specified, TRACE generates a verbose report with a limit of five errors per constraint. The report displays in the EPIC history area.

To run the TRACE from the EPIC command line follow these steps.

  1. Select the constraint(s) that you want TRACE to analyze according to the instructions in the “Selecting Constraints for Timing Analysis” section.

  2. Select Post Cmd from the View menu to bring up the EPIC Command Line dialog box.

  3. Type trace and any desired optional commands.

    When TRACE completes its analysis, the TRACE Summary dialog box appears as shown in the “TRACE Summary Dialog Box” figure.

For additional timing information on any of the constraints, click on the listed constraint. The TRACE Error dialog box appears, as shown in the “TRACE Error Dialog Box” figure.


NOTE

Another way of invoking the TRACE Error dialog box is to use the Post command. See the “Post” section of the “Command Line Syntax” chapter.


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