IFDI_1

Input D Flip-Flop with Inverted Clock (Asynchronous Preset)

The IFDI_1 D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes data entering the chip. The data on input D is loaded into the flip-flop during the High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or through another external pin.

The flip-flop is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR (XC4000, Spartans) default to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.

For information on legal IFDI, IFDI_1, ILDI, and ILDI_1 combinations, refer to the “ILDI” section.

Inputs		Outputs
D	C	Q
0		0
1		1

Figure 6.12 IFDI_1 Implementation XC4000, Spartans

Figure 6.13 IFDI_1 Implementation Virtex