Functional simulation provides an effective means of identifying logic errors in designs not yet implemented into a Xilinx device. The simulator tests the logic in the design using unit delays instead of timing information, not available because placing and routing has yet to occur on the design. Simulate the functionality after entering your design to verify correct circuit logic before mapping, placing, and routing take place. Finding errors before routing your design saves debugging time later in the design process.
This chapter describes how to prepare a simulation network for a functional simulation in the Viewlogic simulation environment. This chapter also describes how to load ViewTrace to view the simulation signals in a waveform format.
However, this chapter does not document specific Viewlogic commands for ViewSim, Speedwave, or ViewTrace. For information regarding the use of these tools, consult the online Viewlogic help files accessible from all of these tools. This chapter contains these sections.
