Additional Implementation Tools

From the Project Manager's Tools menu, you can select Tools Implementation to access the additional implementation tools described below.

Flow Engine Controls

You can invoke and run the Flow Engine manually by selecting Tools Implementation Flow Engine. Be aware that when invoked from the Tools menu, Flow Engine process is not under Project Management control.

Controlling Flow Engine Steps

If you want to implement your design in separate steps instead of automatically with the Implementation phase button, use the following procedure.

1. Create a new revision by selecting Project Create Revision. In the New Revision dialog box, you can accept the defaults or change the target device, speed, and revision name. Click OK to create the revision.
   
   
2. In the Project Manager Versions tab, select the revision.
   
   
3. Select Tools Implementation Flow Engine from the Project Manager's menu bar.
   
   
4. If you want to modify the implementation option settings, select Setup Options from the menu in the Flow Engine to access the Options dialog box.
   
   
5. Set the appropriate options in the Options dialog box.
   
   Refer to the “Selecting Options” section for information on the Options dialog box.
   
   
6. Click OK to return to the Flow Engine.
   
   
7. To start the Flow Engine, do one of the following.
   
   
   • In the Flow Engine window, select Flow Run.
     
     
   • Select Flow Step to single step through the implementation process.
     
     

Optionally, you can select Setup Stop After and select where to stop processing.

Running Re-Entrant Routing on FPGAs

You can use re-entrant routing to further route an already routed design. The design maintains its current routing and additional routing is added. You can reroute connections by running cost-based cleanup, delay-based cleanup, and additional re-entrant route passes. Cleanup passes attempt to minimize the delays on all nets and decrease the number of routing resources used. Cost-based cleanup routing is faster while delay-based cleanup is more intensive.

Re-entrant routing offers the following advantages.

• Cleanup passes significantly reduce delays, especially on non-timing driven runs.
  
  
• For timing-driven runs, cleanup passes can improve timing on elements not covered by timing constraints.
  
  
• For designs which do not meet timing goals by a narrow margin, delay-based cleanup passes can reorganize routing so that additional re-entrant route passes enable the design to meet timing goals.
  
  

NOTE

Re-entrant Routing is supported for the FPGA device families only.

Use the following procedure to perform Re-Entrant Routing.

1. In the Project Manager Versions tab, select an implemented revision.
   
   
2. Select Tools Implementation Flow Engine from the Project Manager's menu bar.
   
   
3. Select Setup FPGA Re-entrant Route from the Flow Engine to access the FPGA Re-entrant Route dialog box.
   
   
   
   
4. Select Allow Re-entrant Routing to route the previously routed design again.
   
   
5. Select a number between 1 and 5 for the Run _ Cost-Based Cleanup Passes field.
   
   These cleanup passes reroute nets if the new routing uses less costly resources than the original configuration. Cost is based on pre-determined cost tables. Cost-based cleanup usually has a faster runtime than the delay-based cleanup, but does not reduce delays as significantly.
   
   

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   NOTE

   If you run both cost-based and delay-based cleanup passes, the cost-based passes run first.

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6. Select a number between 1 and 5 for the Run _ Delay-Based Cleanup Passes field.
   
   These cleanup passes reroute nets if new routing will minimize the delay for a given connection. Delay-based cleanup usually produces faster in-circuit performance.
   
   
7. Select a number between 1 to 2000 for the Run _ Re-entrant Route Passes field to run additional re-entrant routing passes.
   
   These passes are either timing driven or non-timing driven depending on whether you specified timing constraints.
   
   
8. Select Use Timespecs During Re-entrant Route if you want to reroute the design within the specified timing constraints in your design file.
   
   
9. Click OK. This causes the Place and Route icon in the Flow Engine to show a loop back arrow and the Re-Entrant route label.
   
   
10. If you are specifying timing or location constraints, you have the option to relax them to give PAR more flexibility. If you modify the UCF file, you must step backwards with the Flow Engine and re-run Translation in order to incorporate the changes.
    
    

Since your design is already implemented, step back to the beginning of Place and Route using the Step Backward button at the bottom of the Flow Engine, and then click the button to start again.

Configuring the Flow

You can configure the implementation flow and control certain aspects of the Flow Engine interface. To configure the flow, use the following procedure.

1. In the Project Manager Versions tab, select an implemented revision (or create a new revision).
   
   
2. Select Tools Implementation Flow Engine from the Project Manager's menu bar.
   
   
3. From the Flow Engine menu, select Setup Advanced to access the Advanced dialog box.
   
   
   
   
4. Select a state from the Implementation State list box to update the Flow Engine as to which implementation state was last completed.
   
   

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   NOTE

   The advanced setting is not used in normal Flow Engine use. It is used if some processing on the design was performed outside of the Project Manager or Flow Engine framework, such as in the EPIC Design Editor. It can also be used if you ran the Flow Engine Step Back button by mistake and want to reset the implementation state to its original state.

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5. Select Use Flashing to Indicate Heartbeat to enable flashing icons to indicate that a process step is being processed. A trade-off of this feature is that flashing icons slow down the implementation process.
   
   
6. Click OK.
   
   

Floorplanner

The Floorplanner is a graphical placement tool that gives you control over placing a design into a target FPGA. You can access the Floorplanner through Tools Implementation Floorplanner on the Project Manager's menu bar.

Floorplanning is an optional methodology to help you improve performance and density of a fully, automatically placed and routed design. Floorplanning is particularly useful on structured designs and data path logic. With the Floorplanner, you see where to place logic in the floorplan for optimal results, placing data paths exactly at the desired location on the die.

With the Floorplanner, you can floorplan your design prior to or after running PAR. In an iterative design flow, you floorplan and place and route, interactively. You can modify the logic placement in the Floorplan window as often as necessary to achieve your design goals. You can save the iterations of your floorplanned design to use later as a constraints file for PAR.

The Floorplanner displays a hierarchical representation of the design in the Design Hierarchy window using hierarchy structure lines and colors to distinguish the different hierarchical levels. The Floorplan window displays the floorplan of the target device into which you place logic from the hierarchy. The following figure shows the windows on the PC version.

Logic symbols represent each level of hierarchy in the Design Hierarchy window. You can modify that hierarchy in the Floorplanner without changing the original design.

You use the mouse to select the logic from the Design Hierarchy window and place it in the FPGA represented in the Floorplan window.

Alternatively, you can invoke the Floorplanner after running the automatic place and route tools to view and possibly improve the results of the automatic implementation.

EPIC Design Viewer/Editor

The Editor for Programmable Integrated Circuits (EPIC) is a graphical application for displaying and configuring FPGAs. You can use EPIC to place and route critical components before running the automatic place and route tools on your designs. You can also use EPIC to manually finish placement and routing if the routing program does not completely route your design. In addition, EPIC reads from and writes to the Physical Constraints File (PCF).

For a description of EPIC, see the DynaText online manual, EPIC Design Editor Reference/User Guide.

You can access EPIC through Tools Implementation EPIC Design Viewer/Editor on the Project Manager's menu bar.

Locking Device Pins

You can automatically generate pin locking constraints in your UCF file for use with other Xilinx implementation tools. Pinout information is taken from a placed NCD file for FPGAs or a fitted GYD file for CPLDs.

To lock device pins, do the following.

1. From the Versions tab in the Project Manager window, select an implementation revision.
   
   
2. Select Tools Implementation Lock Device Pins from the Project Manager menu bar.
   
   
3. When the Lock Pins Status confirmation dialog box appears, click OK or click View Lock Pins Report to view the report.
   
   Pin locking constraints that created with this command are added to your UCF file in the PINLOCK section.
   
   

If you want to view the report after you have dismissed the Lock Pins Status dialog box, use Tools Implementation Lock Pins Report from the Project Manager.

Constraints Editor

The Xilinx Constraints Editor is a Graphical User Interface (GUI) that provides you with a convenient way to create user constraints files without having to learn constraints syntax. You can use the blank .ucf file created by the Project Manager for your project with the Constraints Editor.

The Constraints Editor interface consists of a main window, three tab windows for creating global, port, and advanced constraints, and a number of dialog boxes.

Invoke the Xilinx Constraints Editor by selecting Start Programs Xilinx Foundation Series Accessories Constraints Editor

Information on the Xilinx Constraints Editor can be found in the Constraints Editor User Guide, an online Dynatext book.