Timing Analyzer

The Timing Analyzer performs static timing analysis of an FPGA or CPLD design. A static timing analysis is a point-to-point analysis of a design network. It does not include insertion of stimulus vectors.The FPGA design must be mapped and can be partially or completely placed, routed, or both. The CPLD design must be completely placed and routed (fitted).

The Timing Analyzer verifies that the delay along a given path or paths meets your specified timing requirements. It organizes and displays data that allows you to analyze the critical paths in a circuit, the cycle time of the circuit, the delay along any specified path, and the paths with the greatest delay. It also provides a quick analysis of the effect of different speed grades on the same design.

The Timing Analyzer works with synchronous systems composed of flip-flops and combinatorial logic. In synchronous designs, the Timing Analyzer takes into account all path delays, including clock-to-Q and setup requirements while calculating the worst-case timing of the design. However, the Timing Analyzer does not perform setup and hold checks. You must use a simulation tool for these checks.

The Timing Analyzer creates timing analysis reports, which you customize by applying filters with the Path Filters menu commands.

For a complete description of the Timing Analyzer, see the DynaText online manual, Timing Analyzer Reference/User Guide.

Post Implementation Static Timing Analysis

Post-implementation timing reports incorporate all delays to provide a comprehensive timing summary. If an implemented design has met all of your timing constraints, then you can proceed by creating configuration data and downloading a device. On the other hand, if you identify problems in the timing reports, you can try fixing the problems by increasing the placer effort level or using re-entrant routing. You can also redesign the logic paths to use fewer levels of logic, tag the paths for specialized routing resources, move to a faster device, or allocate more time for the paths.

Edit the Implementation template (from the Project Manager, select Implementation Options Implementation - Edit Template) to modify the placer effort level. For information on re-entrant routing, see the “Running Re-Entrant Routing on FPGAs” section in the “An Introduction to Design Implementation chapter.

Summary Timing Reports

Summary reports show timing constraint performance and clock performance. Implementing a design in the Flow Engine can automatically generate summary timing reports. To create summary timing reports, perform the following steps.

Summary reports show timing constraint performance and clock performance. Implementing a design in the Flow Engine can automatically generate summary timing reports. To create summary timing reports, perform the following steps:

1. Open the Options dialog box (Implementation Implementation Options) from the Project Manager) and select Edit Template for the Implementation template.
   
   
2. Select the Timing Reports tab.
   
   
3. For a post-map report, select Produce Logic Level Timing Report. For a post-PAR report select Produce Post Layout Timing Report.
   
   
4. To modify the reports to highlight path delays or paths that have failed timing constraints, select a report format.
   
   
5. After MAP or PAR has completed, the respective timing reports appear in the Report Browser.
   
   

Detailed Timing Analysis

To perform detailed timing analysis, select Tools Simulation/Verification Interactive Timing Analyzer from the Project Manager menu. You can specify specific paths for analysis, discover paths not affected by timing constraints, and analyze the timing performance of the implementation based on another speed grade. For path analysis, perform the following:

1. Choose sources. From the Timing Analyzer menu, select Path Filters Path Custom Filters Select Sources.
   
   
2. Choose destinations. From the Timing Analyzer menu, select Path Filters Path Custom Filters Select Destinations.
   
   
3. To create a report, select one of the options under the Analyze menu.
   
   

To switch speed grades, select Options Speed Grade. After a new speed grade is selected, all new Timing Analyzer reports will be based on the design running with new speed grade delays. The design does not have to be re-implemented, because the new delays are read from a separate data file.