Timing Simulation

Timing simulation verifies that your design runs at the desired speed for your device under worst-case conditions. It can verify timing relationships and determine the critical paths for the design under worst-case conditions. It can also determine whether the design contains set-up or hold violations.

The procedures for functional and timing simulation are nearly identical. Functional simulation is performed before the design is placed and routed and simulates only the functionality of the logic in the design. Timing simulation is performed after the design is placed and routed and uses timing information based on the delays in the placed and routed design. Timing simulation describes the circuit behavior far more accurately than Functional simulation.

Like functional simulation, you must use input stimulus to run the simulation. To create stimulus, refer to the “Functional Simulation” chapter.

NOTE

Naming the nets during your design entry is very important for both functional and timing simulation. This allows you to find the nets in the simulations more easily than looking for a machine-generated name

Generating a Timing-annotated Netlist

Before performing timing simulation on your design, you must generate a timing-annotated netlist by implementing the design as follows.

1. Within the Project Manager, click the Implementation icon.
   
   
   1. For Schematic Flow projects, this opens the Implement Design dialog box.
      
      
   2. For HDL Flow projects, this opens the Synthesis/Implementation dialog box.
      
      
2. Click the Options button. This opens the Options dialog box.
   
   
3. Verify that the Simulation Template is Foundation EDIF. (Change it to Foundation EDIF, if necessary.)
   
   
4. In the Options dialog box under Optional Targets, select Produce Timing Simulation Data and then click OK.
   
   
5. Implement the design.
   
   
   1. For Schematic Flow projects, click Run in the Implement Design dialog box.
      
      
   2. For HDL Flow projects, click OK in the Synthesis/Implementation dialog box.
      
      

Basic Timing Simulation Process

After the design has been implemented and timing simulation data produced as described in the “Generating a Timing-annotated Netlist” section, you can perform a timing simulation. This section describes the basic steps to perform timing simulation.

1. Open the Timing Simulator by clicking the Timing Simulation icon on the Verification phase button.
   
   
   
   
2. The implementation timing netlist is loaded into the simulator. The Waveform View window displays on top of the Logic Simulator window as shown in the following figure.
   
   
   
   
3. Simulate the design as described in the “Functional Simulation” chapter. Although the procedure is the same for functional and timing simulation, you are now simulating based on a design with worst-case delays in the timing simulator.
   
   
4. Use the controls from the Simulator window to verify your design.