For schematic and HDL designs, functional simulation is performed before design implementation to verify that the logic you created is correct. Your design methodology determines when you perform functional simulation. Generally, for Schematic Flow projects, you can perform functional simulation directly after you have completed your design within the design entry tools. For HDL Flow projects, you perform functional simulation after the design has been entered and synthesized. However, if your design contains underlying netlists (XNF or EDIF), the design must first be “translated” in the Implementation phase in order to merge these additional netlists.
This chapter contains the following sections:
