Overview

Design verification is the process of testing the functionality and performance of your design. Design verification should occur throughout your design process. Foundation supports three complementary methods for design verification. These are described below.

• Simulation
  
  You can perform simulations to determine if the timing requirements and functionality of your design have been met.
  
  
  • Functional Simulation can be performed in Schematic Flow projects immediately after design entry and in HDL Flow projects after synthesis. Refer to the “Functional Simulation” chapter for information on Functional Simulation.
    
    
  • Timing Simulation is performed during the Implementation phase. The “Timing Simulation” section of this chapter discusses design verification using Timing Simulation.
    
    
• Static timing analysis
  
  Static timing analysis is best for quick timing checks of your design.
  
  
  • For Foundation Express users, the Express Time Tracker provides post-synthesis, pre-implementation timing analysis for HDL Flow projects. Refer to “Express Time Tracker^™ (Optional)” section of the “Design Methodologies - HDL Flow” chapter for information.
    
    
  • For Schematic Flow projects and HDL Flow projects, static timing analysis can be done at two different stages of the Implementation phase for FPGA devices: after Map or after Place and Route. It can be done after Fit for CPLDs. Refer to the “Timing Analyzer” section in this chapter for information on static timing analysis within the Implementation phase.
    
    
• In-circuit verification
  
  As a final test, you can verify how your design performs in the target application. In-circuit verification tests the circuit under typical operating conditions. To perform in-circuit verification, you download your design bitstream into a device with the Xilinx XChecker cable. Refer to “In-Circuit Verification” in the Device Programming section of this chapter for information.
  
  

When the design meets your requirements, the last step in its processing is downloading the design and programming the target device.