The Project Manager, the overall project management tool, contains the Foundation Series tools used in the design process. The “Project Manager - Schematic Flow” figure and the “Project Manager - HDL Flow” figure illustrate the tools accessible for the two Foundation 1.5 project flow types. It is through the Project Manager that you access the tools for the design process from design entry tools to device programming.
The Project Manager performs the following functions:
The three main regions of the Project Manager are discussed in the following sections
Foundation organizes related files into a distinct logical unit called a project. Related files include the following:
Two tabs in the Hierarchy Browser area on the Project Manager window keep track of these files. The Hierarchy Browser is an interactive area in addition to a display area. You can open the listed files and versions/revisions by double clicking on them in the Hierarchy Browser - the application that is associated with the file type is invoked. For example, if you double click on a schematic file, the Schematic Editor displays the schematic file. You can also access menus listing the functions you can perform on the displayed items by right clicking on the item.
The Hierarchy Browser's Files and Version tabs are summarized in the following sections. To learn more about how to use the hierarchy browser, select Help 
Foundation Help Contents Project Manager Hierarchy Browser.
The Files tab displays the hierarchy of the project files, project libraries, and external files. From this tab you can add, remove, or reorder the displayed files and libraries as well as open applications associated with them.
For new projects, the Project Manager automatically creates the following files:
A Foundation project always has one or more “top-level” design file(s). In a Schematic Flow project, you can see what the top-level designs in the project are by looking at the top level of the Hierarchy Browser. In a Schematic Flow project, all top-level files must be schematics, state diagrams, or ABEL files. In an HDL Flow project, you designate the top-level entity (VHDL) or module (Verilog) at the time of synthesis. The list of entities/modules is automatically generated from the list of HDL source files that have been added to the project. The added HDL design files are displayed in the File tab of the Hierarchy Browser and can be VHDL or Verilog files.
The following table shows some the of common project files included in the Hierarchy Browser, their extensions, and the Foundation tool that creates them.
| Extension | File Type | Created By |
|---|---|---|
| .pdf | Project description file | Project Manager |
| .sch | Schematic source file | Schematic Capture |
| .v | Verilog source file | HDL Editor |
| .vhd | VHDL source file | HDL Editor |
| .abl | XABEL source file | HDL Editor |
| .asf | FSM (ABEL) source file | FSM Editor |
| .ucf | User constraints file | Project Manager |
| .tve | Test vector file | Logic Simulator |
For detailed information about the project files, libraries, and other project information, refer to the online help by selecting Help Foundation Help Contents Foundation Configuration Information.
The Versions tab displays the revisions and versions of the chip implementations of the design. For a newly created project, this tab is empty.
Project management consists of control over design versions and revisions. A version represents an input design netlist. Each time a change is made to the source design, such as logic being added to or removed from the schematic or the HDL source being modified, a new version may be created. A revision represents an implementation on a given version, usually with new implementation options such as different placement or router effort level.
The Foundation 1.5 Project Manager's project flowchart area contains four tabs that allow you to obtain current information about your current project and facilitate the design process.
The Flow tab displays the project flowchart. You use the buttons on the flowchart to perform steps in the design flow, from design entry through device programming. The buttons included in the flowchart in this area depend on whether you have a Schematic Flow project or an HDL Flow project (see the “Project Manager - Schematic Flow” figure and the “Project Manager - HDL Flow” figure).
When you start programs from the project flowchart, the Project Manager automatically controls the transfer of input and output data (files) between the applications. It performs the necessary steps to take the design to the point you requested.
In addition to the project flowchart, the Project Manager includes a number of alternative ways to run the Foundation application tools. You can access tools by right-clicking items listed in the Hierarchy Browser area. Or, you can use the Tools menus in the Project Manager Toolbar to access submenus for Design Entry, Simulation/Verification, Implementation, and Device Programming tools. It is also possible to start the Foundation applications directly from the Windows environment. The latter method is not recommended because, depending on the application, the Project Manager may not be started and would not be available to track the project properly.
The Contents tab displays info related to the object currently selected (file, library, etc.) from the hierarchy tree on the Files tab. It displays the full pathname of the object selected as well as the date the object was last modified.
Select this tab to access and display reports that have been generated in the design process.
Using the Synthesis tab, you can update or synthesize VHDL, Verilog, ABEL, and State Machine macros. Refer to the “Synthesis Tools” section later is this chapter for more information on this tab. (This tab is unnecessary in an HDL Flow project because the entire project is synthesized.)
The tabs included in the Messages area display general project messages and specific HDL processing messages.
The Console tab displays the contents of the project log.
This tab displays any errors encountered during HDL source file analysis, for the object selected in the Hierarchy Browser.
This tab displays warnings generated during HDL source file processing, for the object selected in the Hierarchy Browser.
This tab displays messages other than errors or warnings generated during HDL source file processing, for the object selected in the Hierarchy Browser.
