Synthesis Tools

Synthesis tools are available for both HDL Flow projects and Schematic Flow projects. If you are using the Base or Standard product, the synthesis tools are available for Finite State Machine and ABEL macros only.

Synthesis Button (HDL Flow)

For design synthesis, Base Express and Foundation Express users have access to FPGA Express from Synopsys, the industry-leading synthesis technology. The Express synthesis tools provide the following capabilities.

• Architecture-specific optimization
  
  
• Verilog, VHDL, or mixed HDL synthesis
  
  
• Automatic Finite State Machine extraction
  
  
• Automatic GSR and I/O insertion
  
  
• Graphical constraints editor. The Express Constraints Editor GUI is available to Foundation Express users only. It is used to set design constraints and view estimated design performance.
  
  

Synthesis Tab (Schematic Flow)

In a Schematic Flow project, the necessary synthesis of any underlying HDL macros in the design can be initiated in the various design entry tools.The Synthesis tab provides the capability to synthesize any or all of the HDL macros (FSM, ABEL, VHDL, or Verilog) in the current project and update the macro symbol and netlist without searching manually through the project and synthesizing/updating them individually.