Design Entry Tools

This section describes the design entry tools. Foundation includes a suite of tools for creating digital circuit designs. These tools provide the following design entry capabilities.

• Top-level schematic entry with the Xilinx Unified libraries components, LogiBLOX symbols, HDL macros, and State Machine macros
  
  
• Top-level HDL design entry and synthesis
  
  
• Top-level HDL designs with schematic-based, state machine, or LogiBLOX instantiated components
  
  
• Finite state machine diagram entry
  
  

Schematic Editor

With the Schematic Editor, you can create multi-sheet hierarchical schematics. The editor features include the following.

• Multiple sheet and hierarchical schematic support
  
  
• Viewlogic schematic import
  
  
• Board-level and PLD schematic support (requires the Active-CAD tool)
  
  
• Export of schematic netlists to XNF, EDIF, VHDL, and Verilog formats
  
  
• Integration with synthesis design tools (HDL Editor and State Diagram editor)
  
  
• Integration with the Logic Simulator
  
  

For detailed information about the Schematic Editor, select Help Foundation Help Contents Schematic Editor. Also, see the “Schematic Design Entry” chapter.

State Editor

State machine designs typically start with the translation of a concept into a “paper design,” usually in the form of a state diagram or a bubble diagram. The paper design is converted to a state table and finally into the source code itself. The State Editor, which allows you to create state machine designs, also supports the following functions:

• Generates behavioral VHDL, Verilog, or ABEL (Schematic Flow only) code from the state diagram
  
  
• Invokes the Express or XABEL compiler to convert the behavioral description into a gate-level netlist
  
  
• Simulates a state diagram macro graphically
  
  

For more information about how to use the State Editor, select Help Foundation Help Contents State Editor.

HDL Editor

The HDL Editor, a text editor, is designed to edit HDL source files created in the VHDL, Verilog, or ABEL (Schematic Flow only) languages. The HDL Editor utilizes syntax coloring for the VHDL, Verilog, and ABEL languages. The HDL Editor allows you to check HDL language syntax as well as create HDL macro symbols for placement on a schematic.

The Language Assistant tool (Tools Language Assistant in the HDL Editor) furnishes the following templates with source code for VHDL, Verilog, and ABEL.

• Language templates with basic language constructs
  
  
• Synthesis templates of functional blocks such as counters, flip-flops, multiplexers, and Xilinx architectural features such as Boundary Scan and RAM
  
  

For detailed information about the HDL Editor, select Help Foundation Help Contents HDL Editor. Also, refer to the “HDL Design Entry and Synthesis” chapter.

Symbol Editor

With the Symbol Editor, you can edit features of component symbols such as pin locations, pin names, pin numbers, pin shape, and pin descriptions.

From the Project Manager, you can access the Symbol Editor by selecting Tools Design Entry Symbol Editor.

For more details on how to use the Symbol Editor, select Help Foundation Help Contents Advanced Tools Symbol Editor.